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000798
2009 Oct 07
1
[LLVMdev] VLIW Scheduling Redux
Have there been any developments in the codegen/scheduling
infrastructure that would invalidate the advice given in this thread
from September 2005?
http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-September/004798.html
-Ken
2012 Jun 06
2
[LLVMdev] Instruction bundles before RA: Rematerialization
...We have a new BE for a VLIW-like processor and I'm currently working on
instruction bundles. Ideally, I'd like to have bundles *before* RA to
model certain constraints, e.g. the exposed one by Tzu-Chien a while ago
in his thread
http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-September/004798.html
In order to build bundles, we have added a new bottom-up MIScheduler,
right after reg coalescing, which behaves much like ScheduleDAGVLIW but
without hazard recognizing. Due to some tricky instructions, we cannot
schedule on the DAG. Bundles are built at exitRegion() in the scheduling
pro...
2012 Jun 06
0
[LLVMdev] Instruction bundles before RA: Rematerialization
...r a VLIW-like processor and I'm currently working on
> instruction bundles. Ideally, I'd like to have bundles *before* RA to
> model certain constraints, e.g. the exposed one by Tzu-Chien a while ago
> in his thread
> http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-September/004798.html
The bundle support in the tree should handle constraints like that. The register allocator basically sees bundles as single instructions when computing interference.
> In order to build bundles, we have added a new bottom-up MIScheduler,
> right after reg coalescing, which behaves muc...
2012 Jun 07
2
[LLVMdev] Instruction bundles before RA: Rematerialization
...and I'm currently
working on
> instruction bundles. Ideally, I'd like to have bundles *before* RA to
> model certain constraints, e.g. the exposed one by Tzu-Chien a
while ago
> in his thread
> http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-September/004798.html
The bundle support in the tree should handle constraints like that.
The register allocator basically sees bundles as single instructions
when computing interference.
> In order to build bundles, we have added a new bottom-up MIScheduler,
> right after reg coalesci...
2012 Jun 07
0
[LLVMdev] Instruction bundles before RA: Rematerialization
...E for a VLIW-like processor and I'm currently working on
> instruction bundles. Ideally, I'd like to have bundles *before* RA to
> model certain constraints, e.g. the exposed one by Tzu-Chien a while ago
> in his thread
> http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-September/004798.html
The bundle support in the tree should handle constraints like that. The register allocator basically sees bundles as single instructions when computing interference.
> In order to build bundles, we have added a new bottom-up MIScheduler,
> right after reg coalescing, which behaves muc...