search for: 000000010

...000: 0f3040000 (d6) pci dev 03:0 bar 14 size 000001000: 0f3050000 (d6) pci dev 02:0 bar 10 size 000000100: 00000c001 (d6) pci dev 04:0 bar 10 size 000000100: 00000c101 (d6) pci dev 04:0 bar 14 size 000000100: 0f3051000 (d6) pci dev 01:2 bar 20 size 000000020: 00000c201 (d6) pci dev 01:1 bar 20 size 000000010: 00000c221 (d6) Multiprocessor initialisation: (d6) - CPU0 ... 39-bit phys ... fixed MTRRs ... var MTRRs [1/8] ... done. (d6) - CPU1 ... 39-bit phys ... fixed MTRRs ... var MTRRs [1/8] ... done. (d6) Writing SMBIOS tables ... (d6) Loading SeaBIOS ... (d6) Creating MP tables ... (d6) Loading ACPI...

...fffff82203e84 cr0: 000000008005003b cr4: 00000000000426e4 (XEN) cr3: 000000049c571000 cr2: 0000000000000028 (XEN) ds: 0000 es: 0000 fs: 0000 gs: 0000 ss: e02b cs: e033 (XEN) Guest stack trace from rsp=ffffffff82203e10: (XEN) 0000000000000000 ffffffff82203f04 0000000000000000 ffffffff8103f261 (XEN) 000000010000e030 0000000000010092 ffffffff82203e58 000000000000e02b (XEN) 0000000000000000 ffffffff8241d460 0000000000000000 0000000000000000 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 (XEN) 0000000000000000 0000000000000000 ffffffff8241d460 ffffffff82203f04 (XEN) ffffffff8...

[disclaimer: I am the author of Rufus] Hi, On 2014.01.15 10:10, Thomas Schmitt wrote: > As producer of MBRs i wonder where that LBA-flag is located. > In bit 0 to bit 6 of byte 446 (where bit 7 means active/bootable) ? I haven't looked at what GParted does, so I may be off mark, but I have a strong suspicion that this LBA "flag" is a fake flag that simply indicates if a

...N) [2013-07-17 19:10:12] HVM17: pci dev 03:0 bar 10 size 000000100: 00000c001 (XEN) [2013-07-17 19:10:12] HVM17: pci dev 04:0 bar 14 size 000000040: 00000c101 (XEN) [2013-07-17 19:10:12] HVM17: pci dev 01:2 bar 20 size 000000020: 00000c141 (XEN) [2013-07-17 19:10:12] HVM17: pci dev 01:1 bar 20 size 000000010: 00000c161 (XEN) [2013-07-17 19:10:12] HVM17: Multiprocessor initialisation: (XEN) [2013-07-17 19:10:12] HVM17: - CPU0 ... 48-bit phys ... fixed MTRRs ... var MTRRs [2/8] ... done. (XEN) [2013-07-17 19:10:12] HVM17: - CPU1 ... 48-bit phys ... fixed MTRRs ... var MTRRs [2/8] ... done. (XEN) [2013-...

...il: libxl_dom.c:195:numa_place_domain: NUMA placement candidate with 1 nodes, 8 cpus and 9050 KB free selected xc: detail: elf_parse_binary: phdr: paddr=0x100000 memsz=0x9efa8 xc: detail: elf_parse_binary: memory: 0x100000 -> 0x19efa8 xc: detail: VIRTUAL MEMORY ARRANGEMENT: Loader: 0000000000100000->000000000019efa8 Modules: 0000000000000000->0000000000000000 TOTAL: 0000000000000000->0000000078000000 ENTRY ADDRESS: 0000000000100000 xc: detail: PHYSICAL MEMORY ALLOCATION: 4KB PAGES: 0x0000000000000200 2MB PAGES: 0x00000000000003bf 1GB PAGES: 0x00000...

...C methods: V2; EDID transfer time: 1 seconds (XEN) Disc information: (XEN) Found 3 MBR signatures (XEN) Found 4 EDD information structures (XEN) Xen-e820 RAM map: (XEN) 0000000000000000 - 000000000009e800 (usable) (XEN) 000000000009e800 - 00000000000a0000 (reserved) (XEN) 00000000000e0000 - 0000000000100000 (reserved) (XEN) 0000000000100000 - 00000000ba9c4000 (usable) (XEN) 00000000ba9c4000 - 00000000bab48000 (reserved) (XEN) 00000000bab48000 - 00000000bab58000 (ACPI data) (XEN) 00000000bab58000 - 00000000bb95b000 (ACPI NVS) (XEN) 00000000bb95b000 - 00000000bca38000 (reserved) (XEN) 00000000...

*RESEND* due to exceeding the mailinglists limit for attachment size. Hi, I''m trying to get secondary vga-passthrough on a HVM guest to work with a AMD HD6570 and the native kernel radeon driver and kernel modesetting. So the guest still gets the emulated stdvga or cirrus device(used in my case here) as primary/boot vga adapter. - When i don''t passthrough the radeon card, the