Displaying 8 results from an estimated 8 matches for "00000000h".
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2015 Feb 13
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...rax+r8*4]
lea r9d, [rcx+1]
mov [rax+r8*4], r9d
cmp ecx, r8d
jge loc_100000F0E
lea r12, [rax+4]
xor r14d, r14d
db 2Eh
nop word ptr [rax+rax+00000000h]
loc_100000E20: ; CODE XREF: _main+216 j
test r15d, r15d
setle cl
cmp r15d, 2
jl short loc_100000E90
test cl, cl
mov r13d, 0
mov r11, r1...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...mov [rax+r8*4], r9d
>> cmp ecx, r8d
>> jge loc_100000F0E
>> lea r12, [rax+4]
>> xor r14d, r14d
>> db 2Eh
>> nop word ptr [rax+rax+00000000h]
>>
>> loc_100000E20: ; CODE XREF: _main+216 j
>> test r15d, r15d
>> setle cl
>> cmp r15d, 2
>> jl short loc_100000E90
>> test cl, cl
&...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...; cmp ecx, r8d
>>>> jge loc_100000F0E
>>>> lea r12, [rax+4]
>>>> xor r14d, r14d
>>>> db 2Eh
>>>> nop word ptr [rax+rax+00000000h]
>>>>
>>>> loc_100000E20: ; CODE XREF: _main+216 j
>>>> test r15d, r15d
>>>> setle cl
>>>> cmp r15d, 2
>>>> jl short loc_100...
2007 Jan 04
2
Automatically choose between 32-bit and 64-bit kernel
...r eax,(1 << 21) ; CPUID bit
+ push eax
+ popfd
+ pushfd
+ pop eax
+ popfd ; Restore the original flags
+ xor eax,ebx
+ jz is_32bit
+;
+; Now check for the 64-bit flag in the CPU features byte ($0000_0001, edx)
+; This is bit 30 for Intel CPUs, and bit 29 for AMD CPUs
+;
+ mov eax, 00000000h ; Find last Intel cpuid #
+ cpuid
+ cmp eax, 00000000h
+ je test_amd
+ mov eax, 00000001h ; Read Intel CPU flags
+ cpuid
+ bt edx, 30 ; 64-bit if bit 30 is set
+ jc is_64bit
+
+test_amd: mov eax, 80000000h ; Find last AMD cpuid #
+ cpuid
+ cmp eax, 80000000h
+ jbe is_32bit
+ mov eax...
2008 Jan 02
0
Fwd: [Workaround] Allocation size has bad value on a MIPS based setup.
...location Size"
field was set to 4503599628419072 (00001000 00001000h). This is
present in any SMB messages featuring a "Allocation size" field.
Using another linux+samba working setup and sniffing SMB messages
again, the "Allocation size" field was set to 1048576 (00001000
00000000h). Which is a fairer value :-)
After a few investigations on the warnings (warning: right, left shift
count >= width of type) when compiling ntrans.c, trans2.c and a few
other files in libsmb, it seems that they come from the macros like
SOFF_T and alike defined in include.h when LARGE_SMB_OFF_T...
2013 Jan 29
3
[PATCH v4 2/2] Xen: Fix VMCS setting for x2APIC mode guest while enabling APICV
The "APIC-register virtualization" and "virtual-interrupt deliver"
VM-execution control has no effect on the behavior of RDMSR/WRMSR if
the "virtualize x2APIC mode" VM-execution control is 0.
When guest uses x2APIC mode, we should enable "virtualize x2APIC mode"
for APICV first.
Signed-off-by: Jiongxi Li <jiongxi.li@intel.com>
diff --git
2008 Aug 10
1
Problems with games
...x65adaa): stub
err:eventlog:ReportEventW L"7"
fixme:advapi:DeregisterEventSource (0xcafe4242) stub
Empire Earth II: Crashes with this:
Code:
EXCEPTION: ACCESS VIOLATION
0x00968b6a: offset 968b6a from [(unknown)]
0x00000005: offset 5 from [(unknown)]
EAX: 01cd9504h ESI: 00000000h
EBX: 00000002h EDI: 01c0b92ch
ECX: 00000000h EBP: 01b6caach
EDX: 00000038h ESP: 00f2f904h
EIP: 00968b6ah
SS: 0000007bh CS: 00000073h
DS: 0000007bh FS: 00000033h
ES: 0000007bh GS: 0000003bh
Flags: 00210246h CF: 0 PF:1 AF:0 ZF:1 SF:0 OF:0
Con...
2008 Jun 27
32
[PATCH][RFC] Support more Capability Structures and Device Specific
I am submitting the patch which supports more Capability Structures
and Device Specific Registers for passthrough device.
In Xen 3.3 unstable, qemu-dm supports Configuration Header, MSI
Capability Structure, and MSI-X Capability Structure. But qemu-dm does
not support PCI Express Capability Structure, Device Specific
Registers, etc (writing them is ignored).
To support various I/O devices, I