Nouveau - Nov 2025 - [PATCH 03/11] gpu: nova-core: support header parsing on Turing/GA100

On Wed, 2025-11-19 at 11:51 +0900, Alexandre Courbot
wrote:
> I'd prefer if we could reason in terms of functionality instead of
> specific chipset versions.
If you can figure it out, I'd be happy to change the code.  I wasn't
being lazy when I made this
comment:

  // There are two versions of Booter, one for Turing/GA100, and another for
  // GA102+.  The extraction of the IMEM sections differs between the two
  // versions.  Unfortunately, the file names are the same, and the headers
  // don't indicate the versions.  The only way to differentiate is by the
Chipset.
> IIUC the relevant factor is that Turing/GA100 have some non-secure
> bootloader code as the entry point of booter, which GA102+ doesn't
> feature as it is capable of starting in secure mode directly (please
> correct me as my understanding is probably incomplete if not outright
> wrong).
That sounds about right.  There are secure and non-secure sections in the
firmware image.
> What is the HW or SW fact that requires this on Turing??
I don't know how to answer that question.  That's just how it's done
on Turing/GA100.  I would
need to start an internal Slack thread to get a better answer, and I don't
really see what it
would gain us.
> Is it linked
> to the fact we need to use PIO for it? What I would like to achieve is
> removing or at least reducing these chipset checks into one single
> point, which in the worst case could be a method of `Chipset` telling us
> which loading method to use. But if we can find a distinguishing factor
> in the parsed by this method, that would be even better.
Both OpenRM and Nouveau use the chipset to gate on how to parse the headers.

On Wed Nov 19, 2025 at 2:16 PM JST, Timur Tabi wrote:
> On Wed, 2025-11-19 at 11:51 +0900, Alexandre Courbot wrote:
>> I'd prefer if we could reason in terms of functionality instead of
>> specific chipset versions.
>
> If you can figure it out, I'd be happy to change the code.  I
wasn't being lazy when I made this
> comment:
>
>   // There are two versions of Booter, one for Turing/GA100, and another
for
>   // GA102+.  The extraction of the IMEM sections differs between the two
>   // versions.  Unfortunately, the file names are the same, and the headers
>   // don't indicate the versions.  The only way to differentiate is by
the Chipset.
Yeah, the answer is definitely not clear for me either. :)
>
>> IIUC the relevant factor is that Turing/GA100 have some non-secure
>> bootloader code as the entry point of booter, which GA102+ doesn't
>> feature as it is capable of starting in secure mode directly (please
>> correct me as my understanding is probably incomplete if not outright
>> wrong).
>
> That sounds about right.  There are secure and non-secure sections in the
firmware image.
>
>> What is the HW or SW fact that requires this on Turing??
>
> I don't know how to answer that question.  That's just how it's
done on Turing/GA100.  I would
> need to start an internal Slack thread to get a better answer, and I
don't really see what it
> would gain us.
I'd like to see if we can get to the bottom of this, mostly because this
post/post GA102 cut is noticeable in at least 2 places:

1. The way FWSEC is loaded,
2. The way booter is loaded and started,

For 1. we have the firmware header version that tells us which method to
use; I wonder if there is some similar information we could use for 2.
in order to avoid hardcoding values.
>
>> Is it linked
>> to the fact we need to use PIO for it? What I would like to achieve is
>> removing or at least reducing these chipset checks into one single
>> point, which in the worst case could be a method of `Chipset` telling
us
>> which loading method to use. But if we can find a distinguishing factor
>> in the parsed by this method, that would be even better.
>
> Both OpenRM and Nouveau use the chipset to gate on how to parse the
headers.
If it comes down to "This is how things are pre and post GA102" (and
the
evidence I have seen to far suggests that unfortunately), then so be it
- we at the very least encode this as a method of `Chipset` to avoid
hardcoding chipset versions in several places.

On 11/18/25 9:16 PM, Timur Tabi wrote:
> On Wed, 2025-11-19 at 11:51 +0900, Alexandre Courbot wrote:
>> I'd prefer if we could reason in terms of functionality instead of
>> specific chipset versions.
> 
> If you can figure it out, I'd be happy to change the code.  I
wasn't being lazy when I made this
> comment:
> 
>    // There are two versions of Booter, one for Turing/GA100, and another
for
>    // GA102+.  The extraction of the IMEM sections differs between the two
>    // versions.  Unfortunately, the file names are the same, and the
headers
>    // don't indicate the versions.  The only way to differentiate is by
the Chipset.
> 
>> IIUC the relevant factor is that Turing/GA100 have some non-secure
>> bootloader code as the entry point of booter, which GA102+ doesn't
>> feature as it is capable of starting in secure mode directly (please
>> correct me as my understanding is probably incomplete if not outright
>> wrong).
> 
> That sounds about right.  There are secure and non-secure sections in the
firmware image.
> 
>> What is the HW or SW fact that requires this on Turing?
> 
> I don't know how to answer that question.  That's just how it's
done on Turing/GA100.  I would
> need to start an internal Slack thread to get a better answer, and I
don't really see what it
> would gain us.
Here, would it be reasonable to just create a tiny HAL-like construct
(a trait, I guess) that has the function to call, and it decides which
behavior to use based on the chipset-selected HAL.

In other words, we know very clearly that we need to call one version of
the function for earlier chips, and the other version of the function for
later chips, and the dividing line is because that behavior changed at
a certain chipset.

I think this HAL-centric, chipset-centric approach is fine for some
things, where we really have no reason to care about the internal details.

For other cases, the functionality based partitioning is probably ideal.

Thoughts?
> 
>> Is it linked
>> to the fact we need to use PIO for it? What I would like to achieve is
>> removing or at least reducing these chipset checks into one single
>> point, which in the worst case could be a method of `Chipset` telling
us
>> which loading method to use. But if we can find a distinguishing factor
>> in the parsed by this method, that would be even better.
> 
> Both OpenRM and Nouveau use the chipset to gate on how to parse the
headers.
Yes. That also carries some weight.

thanks,
-- 
John Hubbard