John Hubbard
2025-Oct-25 00:14 UTC
[PATCH 0/2] gpu: nova: add boot42 support for next-gen GPUs
NVIDIA GPUs are moving away from using NV_PMC_BOOT_0 to contain architecture and revision details, and will instead use NV_PMC_BOOT_42 in the future. NV_PMC_BOOT_0 will be zeroed out. Change the selection logic in Nova so that it will claim Turing and later GPUs. This will work for the foreseeable future, without any further code changes here, because all NVIDIA GPUs are considered, from the oldest supported on Linux (NV04), through the future GPUs. Add some comment documentation to explain, chronologically, how boot0 and boot42 change with the GPU eras, and how that affects the selection logic. Also, remove a couple of types: Spec and Revision. That deletes a net total of 33 lines of code and simplifies that area of code. It also simplifies the subsequent boot42 support diffs. This is based on today's drm-rust-next, which in turn is based on Linux 6.18-rc2. John Hubbard (2): gpu: nova: remove Spec and Revision types gpu: nova: add boot42 support for next-gen GPUs drivers/gpu/nova-core/gpu.rs | 120 ++++++++++++++++++++-------------- drivers/gpu/nova-core/regs.rs | 28 ++++++++ 2 files changed, 98 insertions(+), 50 deletions(-) base-commit: d3917368ebc5cd89d7d08eab4673e5c4c73ff42f -- 2.51.1
In the fullness of time, it has become clear that these two types are
not actually needed for anything, after all. Remove them both, and use
boot0.chipset directly, instead.
This deletes a net total of 33 lines of code and simplifies the code as
well.
Signed-off-by: John Hubbard <jhubbard at nvidia.com>
---
drivers/gpu/nova-core/gpu.rs | 67 +++++++++---------------------------
1 file changed, 17 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index af20e2daea24..a8a993424771 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -129,48 +129,10 @@ fn try_from(value: u8) -> Result<Self> {
}
}
-pub(crate) struct Revision {
- major: u8,
- minor: u8,
-}
-
-impl Revision {
- fn from_boot0(boot0: regs::NV_PMC_BOOT_0) -> Self {
- Self {
- major: boot0.major_revision(),
- minor: boot0.minor_revision(),
- }
- }
-}
-
-impl fmt::Display for Revision {
- fn fmt(&self, f: &mut fmt::Formatter<'_>) ->
fmt::Result {
- write!(f, "{:x}.{:x}", self.major, self.minor)
- }
-}
-
-/// Structure holding the metadata of the GPU.
-pub(crate) struct Spec {
- chipset: Chipset,
- /// The revision of the chipset.
- revision: Revision,
-}
-
-impl Spec {
- fn new(bar: &Bar0) -> Result<Spec> {
- let boot0 = regs::NV_PMC_BOOT_0::read(bar);
-
- Ok(Self {
- chipset: boot0.chipset()?,
- revision: Revision::from_boot0(boot0),
- })
- }
-}
-
/// Structure holding the resources required to operate the GPU.
#[pin_data]
pub(crate) struct Gpu {
- spec: Spec,
+ chipset: Chipset,
/// MMIO mapping of PCI BAR 0
bar: Arc<Devres<Bar0>>,
/// System memory page required for flushing all pending GPU-side memory
writes done through
@@ -191,16 +153,21 @@ pub(crate) fn new<'a>(
devres_bar: Arc<Devres<Bar0>>,
bar: &'a Bar0,
) -> impl PinInit<Self, Error> + 'a {
+ let boot0 = regs::NV_PMC_BOOT_0::read(bar);
+
try_pin_init!(Self {
- spec: Spec::new(bar).inspect(|spec| {
+ chipset: {
+ let chipset = boot0.chipset()?;
dev_info!(
pdev.as_ref(),
- "NVIDIA (Chipset: {}, Architecture: {:?}, Revision:
{})\n",
- spec.chipset,
- spec.chipset.arch(),
- spec.revision
+ "NVIDIA (Chipset: {}, Architecture: {:?}, Revision:
{:x}.{:x})\n",
+ chipset,
+ chipset.arch(),
+ boot0.major_revision(),
+ boot0.minor_revision()
);
- })?,
+ chipset
+ },
// We must wait for GFW_BOOT completion before doing any
significant setup on the GPU.
_: {
@@ -208,21 +175,21 @@ pub(crate) fn new<'a>(
.inspect_err(|_| dev_err!(pdev.as_ref(), "GFW boot did
not complete"))?;
},
- sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar,
spec.chipset)?,
+ sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar,
boot0.chipset()?)?,
gsp_falcon: Falcon::new(
pdev.as_ref(),
- spec.chipset,
+ boot0.chipset()?,
bar,
- spec.chipset > Chipset::GA100,
+ boot0.chipset()? > Chipset::GA100,
)
.inspect(|falcon| falcon.clear_swgen0_intr(bar))?,
- sec2_falcon: Falcon::new(pdev.as_ref(), spec.chipset, bar, true)?,
+ sec2_falcon: Falcon::new(pdev.as_ref(), boot0.chipset()?, bar,
true)?,
gsp <- Gsp::new(),
- _: { gsp.boot(pdev, bar, spec.chipset, gsp_falcon, sec2_falcon)? },
+ _: { gsp.boot(pdev, bar, boot0.chipset()?, gsp_falcon,
sec2_falcon)? },
bar: devres_bar,
})
--
2.51.1
John Hubbard
2025-Oct-25 00:14 UTC
[PATCH 2/2] gpu: nova: add boot42 support for next-gen GPUs
NVIDIA GPUs are moving away from using NV_PMC_BOOT_0 to contain
architecture and revision details, and will instead use NV_PMC_BOOT_42
in the future. NV_PMC_BOOT_0 will be zeroed out.
Change the selection logic in Nova so that it will claim Turing and
later GPUs. This will work for the foreseeable future, without any
further code changes here, because all NVIDIA GPUs are considered, from
the oldest supported on Linux (NV04), through the future GPUs.
Add some comment documentation to explain, chronologically, how boot0
and boot42 change with the GPU eras, and how that affects the selection
logic.
Signed-off-by: John Hubbard <jhubbard at nvidia.com>
---
drivers/gpu/nova-core/gpu.rs | 69 +++++++++++++++++++++++++++++++----
drivers/gpu/nova-core/regs.rs | 28 ++++++++++++++
2 files changed, 89 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index a8a993424771..a00036721247 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -155,16 +155,67 @@ pub(crate) fn new<'a>(
) -> impl PinInit<Self, Error> + 'a {
let boot0 = regs::NV_PMC_BOOT_0::read(bar);
+ // "next-gen" GPUs (some time after Blackwell) will zero out
boot0, and put the architecture
+ // details in boot42 instead. Avoid reading boot42 unless we are in
that case.
+ let boot42 = if boot0.is_next_gen() {
+ Some(regs::NV_PMC_BOOT_42::read(bar))
+ } else {
+ None
+ };
+
try_pin_init!(Self {
chipset: {
- let chipset = boot0.chipset()?;
+ // Some brief notes about boot0 and boot42, in chronological
order:
+ //
+ // NV04 through Volta:
+ //
+ // Not supported by Nova. boot0 is necessary and sufficient
to identify these
+ // GPUs. boot42 may not even exist on some of these GPUs.
+ //
+ // Turing through Blackwell:
+ //
+ // Supported by both Nouveau and Nova. boot0 is still
necessary and sufficient
+ // to identify these GPUs. boot42 exists on these GPUs but
we don't need to use
+ // it.
+ //
+ // Future "next-gen" GPUs:
+ //
+ // Only supported by Nova. Boot42 has the architecture
details, boot0 is zeroed
+ // out.
+
+ // NV04, the very first NVIDIA GPU to be supported on Linux, is
identified by a
+ // specific bit pattern in boot0. Although Nova does not
support NV04 (see above),
+ // it is possible to confuse NV04 with a "next-gen"
GPU. Therefore, return early if
+ // we specifically detect NV04, thus simplifying the remaining
selection logic.
+ if boot0.is_nv04() {
+ Err(ENODEV)?
+ }
+
+ // Now that we know it is something more recent than NV04, use
boot42 if we
+ // previously determined that boot42 was both valid and
relevant, and boot0
+ // otherwise.
+ let (chipset, major_rev, minor_rev) = if let Some(boot42) =
boot42 {
+ (
+ boot42.chipset()?,
+ boot42.major_revision(),
+ boot42.minor_revision(),
+ )
+ } else {
+ // Current/older GPU: use BOOT0
+ (
+ boot0.chipset()?,
+ boot0.major_revision(),
+ boot0.minor_revision(),
+ )
+ };
+
dev_info!(
pdev.as_ref(),
"NVIDIA (Chipset: {}, Architecture: {:?}, Revision:
{:x}.{:x})\n",
chipset,
chipset.arch(),
- boot0.major_revision(),
- boot0.minor_revision()
+ major_rev,
+ minor_rev
);
chipset
},
@@ -175,21 +226,23 @@ pub(crate) fn new<'a>(
.inspect_err(|_| dev_err!(pdev.as_ref(), "GFW boot did
not complete"))?;
},
- sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar,
boot0.chipset()?)?,
+ sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar, *chipset)?,
gsp_falcon: Falcon::new(
pdev.as_ref(),
- boot0.chipset()?,
+ *chipset,
bar,
- boot0.chipset()? > Chipset::GA100,
+ *chipset > Chipset::GA100,
)
.inspect(|falcon| falcon.clear_swgen0_intr(bar))?,
- sec2_falcon: Falcon::new(pdev.as_ref(), boot0.chipset()?, bar,
true)?,
+ sec2_falcon: Falcon::new(pdev.as_ref(), *chipset, bar, true)?,
gsp <- Gsp::new(),
- _: { gsp.boot(pdev, bar, boot0.chipset()?, gsp_falcon,
sec2_falcon)? },
+ _: {
+ gsp.boot(pdev, bar, *chipset, gsp_falcon, sec2_falcon)?
+ },
bar: devres_bar,
})
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 206dab2e1335..bcd0834c500b 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -25,6 +25,19 @@
});
impl NV_PMC_BOOT_0 {
+ pub(crate) fn is_nv04(self) -> bool {
+ // The very first supported GPU was NV04, and it is identified by a
specific bit pattern in
+ // boot0. This provides a way to check for that, which in turn is
required in order to avoid
+ // confusing future "next-gen" GPUs with NV04.
+ self.architecture_0() == 0 && (self.0 & 0xff00fff0) ==
0x20004000
+ }
+
+ pub(crate) fn is_next_gen(self) -> bool {
+ // "next-gen" GPUs (some time after Blackwell) will set
`architecture_0` to 0, and put the
+ // architecture details in boot42 instead.
+ self.architecture_0() == 0 && !self.is_nv04()
+ }
+
/// Combines `architecture_0` and `architecture_1` to obtain the
architecture of the chip.
pub(crate) fn architecture(self) -> Result<Architecture> {
Architecture::try_from(
@@ -43,6 +56,21 @@ pub(crate) fn chipset(self) -> Result<Chipset> {
}
}
+register!(NV_PMC_BOOT_42 @ 0x00000108, "Extended architecture
information" {
+ 7:0 implementation as u8, "Implementation version of the
architecture";
+ 15:8 architecture as u8, "Architecture value";
+ 19:16 minor_revision as u8, "Minor revision of the chip";
+ 23:20 major_revision as u8, "Major revision of the chip";
+});
+
+impl NV_PMC_BOOT_42 {
+ pub(crate) fn chipset(self) -> Result<Chipset> {
+ let arch = Architecture::try_from(self.architecture())?;
+ let chipset_value = ((arch as u32) << 8) |
u32::from(self.implementation());
+ Chipset::try_from(chipset_value)
+ }
+}
+
// PBUS
register!(NV_PBUS_SW_SCRATCH @ 0x00001400[64] {});
--
2.51.1