Alistair Popple
2025-Aug-27 08:20 UTC
[PATCH 08/10] gpu: nova-core: falcon: Add support to check if RISC-V is active
From: Joel Fernandes <joelagnelf at nvidia.com> Add definition for RISCV_CPUCTL register and use it in a new falcon API to check if the RISC-V core of a Falcon is active. It is required by the sequencer to know if the GSP's RISCV processor is active. Signed-off-by: Joel Fernandes <joelagnelf at nvidia.com> --- drivers/gpu/nova-core/falcon.rs | 8 ++++++++ drivers/gpu/nova-core/regs.rs | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 7bd13481a6a37..8c4faff043455 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -610,4 +610,12 @@ pub(crate) fn signature_reg_fuse_version( self.hal .signature_reg_fuse_version(self, bar, engine_id_mask, ucode_id) } + + /// Check if the RISC-V core is active. + /// + /// Returns `true` if the RISC-V core is active, `false` otherwise. + pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> Result<bool> { + let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID); + Ok(cpuctl.active_stat()) + } } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 0585699ae9511..5df6a2bf42ad9 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -324,6 +324,11 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { // PRISCV +register!(NV_PRISCV_RISCV_CPUCTL @ PFalconBase[0x00001388] { + 7:7 active_stat as bool; + 0:0 halted as bool; +}); + register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalconBase[0x00001668] { 0:0 valid as bool; 4:4 core_select as bool => PeregrineCoreSelect; -- 2.47.2
Timur Tabi
2025-Aug-29 18:48 UTC
[PATCH 08/10] gpu: nova-core: falcon: Add support to check if RISC-V is active
On Wed, 2025-08-27 at 18:20 +1000, Alistair Popple wrote:> +??? pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> Result<bool> { > +??????? let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID); > +??????? Ok(cpuctl.active_stat()) > +??? }I think this should return just bool instead of Result<bool>
Alistair Popple
2025-Sep-02 00:08 UTC
[PATCH 08/10] gpu: nova-core: falcon: Add support to check if RISC-V is active
On 2025-08-30 at 04:48 +1000, Timur Tabi <ttabi at nvidia.com> wrote...> On Wed, 2025-08-27 at 18:20 +1000, Alistair Popple wrote: > > +??? pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> Result<bool> { > > +??????? let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID); > > +??????? Ok(cpuctl.active_stat()) > > +??? } > > I think this should return just bool instead of Result<bool>Agreed. And looking at some of the other sequencer/falcon code in Joel's series I believe similar comments apply there. I assume something changed with the register reading code to make this possible.
Timur Tabi
2025-Sep-19 23:05 UTC
[PATCH 08/10] gpu: nova-core: falcon: Add support to check if RISC-V is active
On Wed, Aug 27, 2025 at 3:28?AM Alistair Popple <apopple at nvidia.com> wrote:> > +register!(NV_PRISCV_RISCV_CPUCTL @ PFalconBase[0x00001388] { > + 7:7 active_stat as bool; > + 0:0 halted as bool; > +});Two more things I've noticed: 1) I think the convention is to list the bits in increase position. That is, 'active_stat' should be on the line below 'halted'' 2) I think that this should actually be PFalcon2Base[0x00000388]