Alexandre Courbot
2025-Jul-18 07:26 UTC
[PATCH v2 16/19] gpu: nova-core: falcon: add distinct base address for PFALCON2
Falcon engines have two distinct register bases: `PFALCON` and
`PFALCON2`. So far we assumed that `PFALCON2` was located at `PFALCON +
0x1000` because that is the case of most engines, but there are
exceptions (NVDEC uses `0x1c00`).
Fix this shortcoming by leveraging the redesigned relative registers
definitions to assign a distinct `PFalcon2Base` base address to each
falcon engine.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
---
drivers/gpu/nova-core/falcon.rs | 7 ++++++-
drivers/gpu/nova-core/falcon/gsp.rs | 6 +++++-
drivers/gpu/nova-core/falcon/sec2.rs | 6 +++++-
drivers/gpu/nova-core/regs.rs | 12 +++++++-----
4 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index
67265a0b5d7b481bbe4c536e533840195207b4bb..2ecdcc6b9b9dea39889eb9e41e3a8293fc56a54d
100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -278,11 +278,16 @@ fn from(value: bool) -> Self {
/// Type used to represent the `PFALCON` registers address base for a given
falcon engine.
pub(crate) struct PFalconBase(());
+/// Type used to represent the `PFALCON2` registers address base for a given
falcon engine.
+pub(crate) struct PFalcon2Base(());
+
/// Trait defining the parameters of a given Falcon engine.
///
/// Each engine provides one base for `PFALCON` and `PFALCON2` registers. The
`ID` constant is used
/// to identify a given Falcon instance with register I/O methods.
-pub(crate) trait FalconEngine: Sync + RegisterBase<PFalconBase> + Sized {
+pub(crate) trait FalconEngine:
+ Sync + RegisterBase<PFalconBase> + RegisterBase<PFalcon2Base> +
Sized
+{
/// Singleton of the engine, used to identify it with register I/O methods.
const ID: Self;
}
diff --git a/drivers/gpu/nova-core/falcon/gsp.rs
b/drivers/gpu/nova-core/falcon/gsp.rs
index
0db9f94036a6a7ced5a461aec2cff2ce246a5e0e..f17599cb49fa1e5077a554dc14b3715aa62a4ebd
100644
--- a/drivers/gpu/nova-core/falcon/gsp.rs
+++ b/drivers/gpu/nova-core/falcon/gsp.rs
@@ -2,7 +2,7 @@
use crate::{
driver::Bar0,
- falcon::{Falcon, FalconEngine, PFalconBase},
+ falcon::{Falcon, FalconEngine, PFalcon2Base, PFalconBase},
regs::{self, macros::RegisterBase},
};
@@ -13,6 +13,10 @@ impl RegisterBase<PFalconBase> for Gsp {
const BASE: usize = 0x00110000;
}
+impl RegisterBase<PFalcon2Base> for Gsp {
+ const BASE: usize = 0x00111000;
+}
+
impl FalconEngine for Gsp {
const ID: Self = Gsp(());
}
diff --git a/drivers/gpu/nova-core/falcon/sec2.rs
b/drivers/gpu/nova-core/falcon/sec2.rs
index
dbc486a712ffce30efa3a4264b0757974962302e..815786c8480db6cb74541d7ab574112baeb816fe
100644
--- a/drivers/gpu/nova-core/falcon/sec2.rs
+++ b/drivers/gpu/nova-core/falcon/sec2.rs
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
-use crate::falcon::{FalconEngine, PFalconBase};
+use crate::falcon::{FalconEngine, PFalcon2Base, PFalconBase};
use crate::regs::macros::RegisterBase;
/// Type specifying the `Sec2` falcon engine. Cannot be instantiated.
@@ -10,6 +10,10 @@ impl RegisterBase<PFalconBase> for Sec2 {
const BASE: usize = 0x00840000;
}
+impl RegisterBase<PFalcon2Base> for Sec2 {
+ const BASE: usize = 0x00841000;
+}
+
impl FalconEngine for Sec2 {
const ID: Self = Sec2(());
}
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index
7a15f391c52c9d0ba3c89094af48998bda82e25e..35d796b744e933ad70245b50e6eff861b429c519
100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -9,7 +9,7 @@
use crate::falcon::{
DmaTrfCmdSize, FalconCoreRev, FalconCoreRevSubversion, FalconFbifMemType,
FalconFbifTarget,
- FalconModSelAlgo, FalconSecurityModel, PFalconBase, PeregrineCoreSelect,
+ FalconModSelAlgo, FalconSecurityModel, PFalcon2Base, PFalconBase,
PeregrineCoreSelect,
};
use crate::gpu::{Architecture, Chipset};
use kernel::prelude::*;
@@ -295,20 +295,22 @@ pub(crate) fn mem_scrubbing_done(self) -> bool {
7:7 allow_phys_no_ctx as bool;
});
-register!(NV_PFALCON2_FALCON_MOD_SEL @ PFalconBase[0x00001180] {
+/* PFALCON2 */
+
+register!(NV_PFALCON2_FALCON_MOD_SEL @ PFalcon2Base[0x00000180] {
7:0 algo as u8 ?=> FalconModSelAlgo;
});
-register!(NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID @ PFalconBase[0x00001198] {
+register!(NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID @ PFalcon2Base[0x00000198] {
7:0 ucode_id as u8;
});
-register!(NV_PFALCON2_FALCON_BROM_ENGIDMASK @ PFalconBase[0x0000119c] {
+register!(NV_PFALCON2_FALCON_BROM_ENGIDMASK @ PFalcon2Base[0x0000019c] {
31:0 value as u32;
});
// TODO[REGA]: this is an array of registers.
-register!(NV_PFALCON2_FALCON_BROM_PARAADDR @ PFalconBase[0x00001210] {
+register!(NV_PFALCON2_FALCON_BROM_PARAADDR @ PFalcon2Base[0x00000210] {
31:0 value as u32;
});
--
2.50.1
John Hubbard
2025-Jul-18 20:23 UTC
[PATCH v2 16/19] gpu: nova-core: falcon: add distinct base address for PFALCON2
On 7/18/25 12:26 AM, Alexandre Courbot wrote: ...> diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/falcon/gsp.rs > index 0db9f94036a6a7ced5a461aec2cff2ce246a5e0e..f17599cb49fa1e5077a554dc14b3715aa62a4ebd 100644 > --- a/drivers/gpu/nova-core/falcon/gsp.rs > +++ b/drivers/gpu/nova-core/falcon/gsp.rs > @@ -2,7 +2,7 @@ > > use crate::{ > driver::Bar0, > - falcon::{Falcon, FalconEngine, PFalconBase}, > + falcon::{Falcon, FalconEngine, PFalcon2Base, PFalconBase}, > regs::{self, macros::RegisterBase}, > }; > > @@ -13,6 +13,10 @@ impl RegisterBase<PFalconBase> for Gsp { > const BASE: usize = 0x00110000;This approach means that the reference manual values such as these, end up being scattered throughout the code base, as magic numbers. I'm thinking that there should be no problem with using a symbol from the manuals, listed in a common area, instead, right?> } > > +impl RegisterBase<PFalcon2Base> for Gsp { > + const BASE: usize = 0x00111000; > +} > + > impl FalconEngine for Gsp { > const ID: Self = Gsp(()); > } > diff --git a/drivers/gpu/nova-core/falcon/sec2.rs b/drivers/gpu/nova-core/falcon/sec2.rs > index dbc486a712ffce30efa3a4264b0757974962302e..815786c8480db6cb74541d7ab574112baeb816fe 100644 > --- a/drivers/gpu/nova-core/falcon/sec2.rs > +++ b/drivers/gpu/nova-core/falcon/sec2.rs > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > > -use crate::falcon::{FalconEngine, PFalconBase}; > +use crate::falcon::{FalconEngine, PFalcon2Base, PFalconBase}; > use crate::regs::macros::RegisterBase; > > /// Type specifying the `Sec2` falcon engine. Cannot be instantiated. > @@ -10,6 +10,10 @@ impl RegisterBase<PFalconBase> for Sec2 { > const BASE: usize = 0x00840000; > } > > +impl RegisterBase<PFalcon2Base> for Sec2 { > + const BASE: usize = 0x00841000; > +}Here are a re more examples of that. thanks, -- John Hubbard