Danilo Krummrich
2025-Feb-04 19:03 UTC
[PATCH v2 1/2] gpu: nova-core: add initial driver stub
Add the initial nova-core driver stub.
nova-core is intended to serve as a common base for nova-drm (the
corresponding DRM driver) and the vGPU manager VFIO driver, serving as a
hard- and firmware abstraction layer for GSP-based NVIDIA GPUs.
The Nova project, including nova-core and nova-drm, in the long term,
is intended to serve as the successor of Nouveau for all GSP-based GPUs.
The motivation for both, starting a successor project for Nouveau and
doing so using the Rust programming language, is documented in detail
through a previous post on the mailing list [1], an LWN article [2] and a
talk from LPC '24.
In order to avoid the chicken and egg problem to require a user to
upstream Rust abstractions, but at the same time require the Rust
abstractions to implement the driver, nova-core kicks off as a driver
stub and is subsequently developed upstream.
Link: https://lore.kernel.org/dri-devel/Zfsj0_tb-0-tNrJy at cassiopeiae/T/#u [1]
Link: https://lwn.net/Articles/990736/ [2]
Link: https://youtu.be/3Igmx28B3BQ?si=sBdSEer4tAPKGpOs [3]
Signed-off-by: Danilo Krummrich <dakr at kernel.org>
---
Changes in v2:
- Fix module name in Kconfig description. (John)
- Expand Kconfig description a bit. (John)
- Expand name for PCI BAR0 region.
- Do not store / print boot0 raw register value. (John)
- Rename CardType to Architecture, rename enum names to represent the
architecture name and adjust enum values according to the register
definition. (John)
- Add an abstraction for register accesses.
- Print chipset, architecture and revision.
- Load bootloader firmware. (Timur)
---
MAINTAINERS | 10 ++
drivers/gpu/Makefile | 1 +
drivers/gpu/nova-core/Kconfig | 14 +++
drivers/gpu/nova-core/Makefile | 3 +
drivers/gpu/nova-core/driver.rs | 47 ++++++++
drivers/gpu/nova-core/gpu.rs | 187 +++++++++++++++++++++++++++++
drivers/gpu/nova-core/nova_core.rs | 15 +++
drivers/gpu/nova-core/regs.rs | 60 +++++++++
drivers/video/Kconfig | 1 +
9 files changed, 338 insertions(+)
create mode 100644 drivers/gpu/nova-core/Kconfig
create mode 100644 drivers/gpu/nova-core/Makefile
create mode 100644 drivers/gpu/nova-core/driver.rs
create mode 100644 drivers/gpu/nova-core/gpu.rs
create mode 100644 drivers/gpu/nova-core/nova_core.rs
create mode 100644 drivers/gpu/nova-core/regs.rs
diff --git a/MAINTAINERS b/MAINTAINERS
index d1086e53a317..f7ddca7de0ef 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7446,6 +7446,16 @@ T: git https://gitlab.freedesktop.org/drm/nouveau.git
F: drivers/gpu/drm/nouveau/
F: include/uapi/drm/nouveau_drm.h
+CORE DRIVER FOR NVIDIA GPUS [RUST]
+M: Danilo Krummrich <dakr at kernel.org>
+L: nouveau at lists.freedesktop.org
+S: Supported
+Q: https://patchwork.freedesktop.org/project/nouveau/
+B: https://gitlab.freedesktop.org/drm/nova/-/issues
+C: irc://irc.oftc.net/nouveau
+T: git https://gitlab.freedesktop.org/drm/nova.git nova-next
+F: drivers/gpu/nova-core/
+
DRM DRIVER FOR OLIMEX LCD-OLINUXINO PANELS
M: Stefan Mavrodiev <stefan at olimex.com>
S: Maintained
diff --git a/drivers/gpu/Makefile b/drivers/gpu/Makefile
index 8997f0096545..36a54d456630 100644
--- a/drivers/gpu/Makefile
+++ b/drivers/gpu/Makefile
@@ -5,3 +5,4 @@
obj-y += host1x/ drm/ vga/
obj-$(CONFIG_IMX_IPUV3_CORE) += ipu-v3/
obj-$(CONFIG_TRACE_GPU_MEM) += trace/
+obj-$(CONFIG_NOVA_CORE) += nova-core/
diff --git a/drivers/gpu/nova-core/Kconfig b/drivers/gpu/nova-core/Kconfig
new file mode 100644
index 000000000000..ad0c06756516
--- /dev/null
+++ b/drivers/gpu/nova-core/Kconfig
@@ -0,0 +1,14 @@
+config NOVA_CORE
+ tristate "Nova Core GPU driver"
+ depends on PCI
+ depends on RUST
+ depends on RUST_FW_LOADER_ABSTRACTIONS
+ default n
+ help
+ Choose this if you want to build the Nova Core driver for Nvidia
+ GPUs based on the GPU System Processor (GSP). This is true for Turing
+ and later GPUs.
+
+ This driver is work in progress and may not be functional.
+
+ If M is selected, the module will be called nova_core.
diff --git a/drivers/gpu/nova-core/Makefile b/drivers/gpu/nova-core/Makefile
new file mode 100644
index 000000000000..2d78c50126e1
--- /dev/null
+++ b/drivers/gpu/nova-core/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_NOVA_CORE) += nova_core.o
diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver.rs
new file mode 100644
index 000000000000..63c19f140fbd
--- /dev/null
+++ b/drivers/gpu/nova-core/driver.rs
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use kernel::{bindings, c_str, pci, prelude::*};
+
+use crate::gpu::Gpu;
+
+#[pin_data]
+pub(crate) struct NovaCore {
+ #[pin]
+ pub(crate) gpu: Gpu,
+}
+
+const BAR0_SIZE: usize = 8;
+pub(crate) type Bar0 = pci::Bar<BAR0_SIZE>;
+
+kernel::pci_device_table!(
+ PCI_TABLE,
+ MODULE_PCI_TABLE,
+ <NovaCore as pci::Driver>::IdInfo,
+ [(
+ pci::DeviceId::from_id(bindings::PCI_VENDOR_ID_NVIDIA,
bindings::PCI_ANY_ID as _),
+ ()
+ )]
+);
+
+impl pci::Driver for NovaCore {
+ type IdInfo = ();
+ const ID_TABLE: pci::IdTable<Self::IdInfo> = &PCI_TABLE;
+
+ fn probe(pdev: &mut pci::Device, _info: &Self::IdInfo) ->
Result<Pin<KBox<Self>>> {
+ dev_dbg!(pdev.as_ref(), "Probe Nova Core GPU driver.\n");
+
+ pdev.enable_device_mem()?;
+ pdev.set_master();
+
+ let bar = pdev.iomap_region_sized::<BAR0_SIZE>(0,
c_str!("nova-core/bar0"))?;
+
+ let this = KBox::pin_init(
+ try_pin_init!(Self {
+ gpu <- Gpu::new(pdev, bar)?,
+ }),
+ GFP_KERNEL,
+ )?;
+
+ Ok(this)
+ }
+}
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
new file mode 100644
index 000000000000..be260a8ffe46
--- /dev/null
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use kernel::{
+ device, devres::Devres, error::code::*, firmware, fmt, pci, prelude::*,
str::CString,
+};
+
+use crate::driver::Bar0;
+use crate::regs;
+use core::fmt;
+
+/// Enum representation of the GPU chipset.
+#[derive(fmt::Debug)]
+pub(crate) enum Chipset {
+ TU102 = 0x162,
+ TU104 = 0x164,
+ TU106 = 0x166,
+ TU117 = 0x167,
+ TU116 = 0x168,
+ GA102 = 0x172,
+ GA103 = 0x173,
+ GA104 = 0x174,
+ GA106 = 0x176,
+ GA107 = 0x177,
+ AD102 = 0x192,
+ AD103 = 0x193,
+ AD104 = 0x194,
+ AD106 = 0x196,
+ AD107 = 0x197,
+}
+
+/// Enum representation of the GPU generation.
+#[derive(fmt::Debug)]
+pub(crate) enum Architecture {
+ Turing = 0x16,
+ Ampere = 0x17,
+ Ada = 0x19,
+}
+
+pub(crate) struct Revision {
+ major: u8,
+ minor: u8,
+}
+
+/// Structure holding the metadata of the GPU.
+pub(crate) struct Spec {
+ chipset: Chipset,
+ arch: Architecture,
+ /// The revision of the chipset.
+ revision: Revision,
+}
+
+/// Structure encapsulating the firmware blobs required for the GPU to operate.
+#[allow(dead_code)]
+pub(crate) struct Firmware {
+ booter_load: firmware::Firmware,
+ booter_unload: firmware::Firmware,
+ bootloader: firmware::Firmware,
+ gsp: firmware::Firmware,
+}
+
+/// Structure holding the resources required to operate the GPU.
+#[allow(dead_code)]
+#[pin_data]
+pub(crate) struct Gpu {
+ spec: Spec,
+ /// MMIO mapping of PCI BAR 0
+ bar: Devres<Bar0>,
+ fw: Firmware,
+}
+
+// TODO replace with something like derive(FromPrimitive)
+impl Chipset {
+ fn from_u32(value: u32) -> Option<Chipset> {
+ match value {
+ 0x162 => Some(Chipset::TU102),
+ 0x164 => Some(Chipset::TU104),
+ 0x166 => Some(Chipset::TU106),
+ 0x167 => Some(Chipset::TU117),
+ 0x168 => Some(Chipset::TU116),
+ 0x172 => Some(Chipset::GA102),
+ 0x173 => Some(Chipset::GA103),
+ 0x174 => Some(Chipset::GA104),
+ 0x176 => Some(Chipset::GA106),
+ 0x177 => Some(Chipset::GA107),
+ 0x192 => Some(Chipset::AD102),
+ 0x193 => Some(Chipset::AD103),
+ 0x194 => Some(Chipset::AD104),
+ 0x196 => Some(Chipset::AD106),
+ 0x197 => Some(Chipset::AD107),
+ _ => None,
+ }
+ }
+}
+
+// TODO:
+// - replace with something like derive(FromPrimitive)
+// - consider to store within Chipset, if arbitrary_enum_discriminant becomes
stable
+impl Architecture {
+ fn from_u32(value: u32) -> Option<Architecture> {
+ match value {
+ 0x16 => Some(Architecture::Turing),
+ 0x17 => Some(Architecture::Ampere),
+ 0x19 => Some(Architecture::Ada),
+ _ => None,
+ }
+ }
+}
+
+impl Revision {
+ fn new(major: u8, minor: u8) -> Self {
+ Self { major, minor }
+ }
+}
+
+impl fmt::Display for Revision {
+ fn fmt(&self, f: &mut fmt::Formatter<'_>) ->
fmt::Result {
+ write!(f, "{:x}.{:x}", self.major, self.minor)
+ }
+}
+
+impl Spec {
+ fn new(bar: &Devres<Bar0>) -> Result<Spec> {
+ let bar = bar.try_access().ok_or(ENXIO)?;
+ let boot0 = regs::Boot0::read(&bar);
+
+ let Some(chipset) = Chipset::from_u32(boot0.chipset()) else {
+ return Err(ENODEV);
+ };
+
+ let Some(arch) = Architecture::from_u32(boot0.arch()) else {
+ return Err(ENODEV);
+ };
+
+ let revision = Revision::new(boot0.major_rev(), boot0.minor_rev());
+
+ Ok(Self {
+ arch,
+ chipset,
+ revision,
+ })
+ }
+}
+
+impl Firmware {
+ fn new(dev: &device::Device, spec: &Spec, ver: &str) ->
Result<Firmware> {
+ let mut chip_name = CString::try_from_fmt(fmt!("{:?}",
spec.chipset))?;
+ chip_name.make_ascii_lowercase();
+
+ let fw_booter_load_path +
CString::try_from_fmt(fmt!("nvidia/{}/gsp/booter_load-{}.bin",
&*chip_name, ver))?;
+ let fw_booter_unload_path +
CString::try_from_fmt(fmt!("nvidia/{}/gsp/booter_unload-{}.bin",
&*chip_name, ver))?;
+ let fw_bootloader_path +
CString::try_from_fmt(fmt!("nvidia/{}/gsp/bootloader-{}.bin",
&*chip_name, ver))?;
+ let fw_gsp_path +
CString::try_from_fmt(fmt!("nvidia/{}/gsp/gsp-{}.bin",
&*chip_name, ver))?;
+
+ let booter_load = firmware::Firmware::request(&fw_booter_load_path,
dev)?;
+ let booter_unload =
firmware::Firmware::request(&fw_booter_unload_path, dev)?;
+ let bootloader = firmware::Firmware::request(&fw_bootloader_path,
dev)?;
+ let gsp = firmware::Firmware::request(&fw_gsp_path, dev)?;
+
+ Ok(Firmware {
+ booter_load,
+ booter_unload,
+ bootloader,
+ gsp,
+ })
+ }
+}
+
+impl Gpu {
+ pub(crate) fn new(pdev: &pci::Device, bar: Devres<Bar0>) ->
Result<impl PinInit<Self>> {
+ let spec = Spec::new(&bar)?;
+ let fw = Firmware::new(pdev.as_ref(), &spec,
"535.113.01")?;
+
+ dev_info!(
+ pdev.as_ref(),
+ "NVIDIA (Chipset: {:?}, Architecture: {:?}, Revision:
{})\n",
+ spec.chipset,
+ spec.arch,
+ spec.revision
+ );
+
+ Ok(pin_init!(Self { spec, bar, fw }))
+ }
+}
diff --git a/drivers/gpu/nova-core/nova_core.rs
b/drivers/gpu/nova-core/nova_core.rs
new file mode 100644
index 000000000000..5d0230042793
--- /dev/null
+++ b/drivers/gpu/nova-core/nova_core.rs
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+
+//! Nova Core GPU Driver
+
+mod driver;
+mod gpu;
+mod regs;
+
+kernel::module_pci_driver! {
+ type: driver::NovaCore,
+ name: "NovaCore",
+ author: "Danilo Krummrich",
+ description: "Nova Core GPU driver",
+ license: "GPL v2",
+}
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
new file mode 100644
index 000000000000..65b46f8a67d3
--- /dev/null
+++ b/drivers/gpu/nova-core/regs.rs
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use crate::driver::Bar0;
+use kernel::revocable::RevocableGuard;
+
+// TODO
+//
+// Create register definitions via generic macros. See task "Generic
register abstraction" in
+// Documentation/gpu/nova/core/todo.rst.
+
+const BOOT0_OFFSET: usize = 0x00000000;
+
+// 3:0
+const BOOT0_MINOR_REV_SHIFT: u8 = 0;
+const BOOT0_MINOR_REV_MASK: u32 = 0x0000000f;
+
+// 7:4
+const BOOT0_MAJOR_REV_SHIFT: u8 = 4;
+const BOOT0_MAJOR_REV_MASK: u32 = 0x000000f0;
+
+// 23:20
+const BOOT0_IMPL_SHIFT: u8 = 20;
+const BOOT0_IMPL_MASK: u32 = 0x00f00000;
+
+// 28:24
+const BOOT0_ARCH_SHIFT: u8 = 24;
+const BOOT0_ARCH_MASK: u32 = 0x1f000000;
+
+// 28:20 - Combine BOOT0_IMPL and BOOT0_ARCH to a new virtual register field.
+const BOOT0_CHIPSET_SHIFT: u8 = BOOT0_IMPL_SHIFT;
+const BOOT0_CHIPSET_MASK: u32 = BOOT0_IMPL_MASK | BOOT0_ARCH_MASK;
+
+pub(crate) struct Boot0(u32);
+
+impl Boot0 {
+ #[inline]
+ pub(crate) fn read(bar: &RevocableGuard<'_, Bar0>) -> Self
{
+ Self(bar.readl(BOOT0_OFFSET))
+ }
+
+ #[inline]
+ pub(crate) fn chipset(&self) -> u32 {
+ (self.0 & BOOT0_CHIPSET_MASK) >> BOOT0_CHIPSET_SHIFT
+ }
+
+ #[inline]
+ pub(crate) fn arch(&self) -> u32 {
+ (self.0 & BOOT0_ARCH_MASK) >> BOOT0_ARCH_SHIFT
+ }
+
+ #[inline]
+ pub(crate) fn minor_rev(&self) -> u8 {
+ ((self.0 & BOOT0_MINOR_REV_MASK) >> BOOT0_MINOR_REV_SHIFT) as
u8
+ }
+
+ #[inline]
+ pub(crate) fn major_rev(&self) -> u8 {
+ ((self.0 & BOOT0_MAJOR_REV_MASK) >> BOOT0_MAJOR_REV_SHIFT) as
u8
+ }
+}
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 44c9ef1435a2..5df981920a94 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -39,6 +39,7 @@ source "drivers/gpu/vga/Kconfig"
source "drivers/gpu/host1x/Kconfig"
source "drivers/gpu/ipu-v3/Kconfig"
+source "drivers/gpu/nova-core/Kconfig"
source "drivers/gpu/drm/Kconfig"
base-commit: 69b8923f5003664e3ffef102e73333edfa2abdcf
--
2.48.1
Danilo Krummrich
2025-Feb-04 19:03 UTC
[PATCH v2 2/2] gpu: nova-core: add initial documentation
Add the initial documentation of the Nova project.
The initial project documentation consists out of a brief introduction
of the project, as well as project guidelines both general and nova-core
specific and a task list for nova-core specifically.
The task list is divided into tasks for general Rust infrastructure
required by the project, tasks regarding GSP enablement and firmware
abstraction, general GPU driver tasks as well as tasks related to
external API design and test infrastructure.
Signed-off-by: Danilo Krummrich <dakr at kernel.org>
---
- Add task "Generic register abstraction".
- Change complexity of "Debugfs abstractions".
---
Documentation/gpu/drivers.rst | 1 +
Documentation/gpu/nova/core/guidelines.rst | 24 ++
Documentation/gpu/nova/core/todo.rst | 445 +++++++++++++++++++++
Documentation/gpu/nova/guidelines.rst | 73 ++++
Documentation/gpu/nova/index.rst | 30 ++
MAINTAINERS | 1 +
6 files changed, 574 insertions(+)
create mode 100644 Documentation/gpu/nova/core/guidelines.rst
create mode 100644 Documentation/gpu/nova/core/todo.rst
create mode 100644 Documentation/gpu/nova/guidelines.rst
create mode 100644 Documentation/gpu/nova/index.rst
diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst
index 1f17ad0790d7..7c2c5dcb5fd4 100644
--- a/Documentation/gpu/drivers.rst
+++ b/Documentation/gpu/drivers.rst
@@ -24,6 +24,7 @@ GPU Driver Documentation
panfrost
panthor
zynqmp
+ nova/index
.. only:: subproject and html
diff --git a/Documentation/gpu/nova/core/guidelines.rst
b/Documentation/gpu/nova/core/guidelines.rst
new file mode 100644
index 000000000000..a389d65d7982
--- /dev/null
+++ b/Documentation/gpu/nova/core/guidelines.rst
@@ -0,0 +1,24 @@
+.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+=========+Guidelines
+=========+
+This documents contains the guidelines for nova-core. Additionally, all common
+guidelines of the Nova project do apply.
+
+Driver API
+=========+
+One main purpose of nova-core is to implement the abstraction around the
+firmware interface of GSP and provide a firmware (version) independent API for
+2nd level drivers, such as nova-drm or the vGPU manager VFIO driver.
+
+Therefore, it is not permitted to leak firmware (version) specifics, through
the
+driver API, to 2nd level drivers.
+
+Acceptance Criteria
+==================+
+- To the extend possible, patches submitted to nova-core must be tested for
+ regressions with all 2nd level drivers.
diff --git a/Documentation/gpu/nova/core/todo.rst
b/Documentation/gpu/nova/core/todo.rst
new file mode 100644
index 000000000000..5e66ec35c5e3
--- /dev/null
+++ b/Documentation/gpu/nova/core/todo.rst
@@ -0,0 +1,445 @@
+.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+========+Task List
+========+
+Tasks may have the following fields:
+
+- ``Complexity``: Describes the required familiarity with Rust and / or the
+ corresponding kernel APIs or subsystems. There are four different
complexities,
+ ``Beginner``, ``Intermediate``, ``Advanced`` and ``Expert``.
+- ``Reference``: References to other tasks.
+- ``Link``: Links to external resources.
+- ``Contact``: The person that can be contacted for further information about
+ the task.
+
+Enablement (Rust)
+================+
+Tasks that are not directly related to nova-core, but are preconditions in
terms
+of required APIs.
+
+FromPrimitive API
+-----------------
+
+Sometimes the need arises to convert a number to a value of an enum or a
+structure.
+
+A good example from nova-core would be the ``Chipset`` enum type, which defines
+the value ``AD102``. When probing the GPU the value ``0x192`` can be read from
a
+certain register indication the chipset AD102. Hence, the enum value ``AD102``
+should be derived from the number ``0x192``. Currently, nova-core uses a custom
+implementation (``Chipset::from_u32`` for this.
+
+Instead, it would be desirable to have something like the ``FromPrimitive``
+trait [1] from the num crate.
+
+Having this generalization also helps with implementing a generic macro that
+automatically generates the corresponding mappings between a value and a
number.
+
+| Complexity: Beginner
+| Link: https://docs.rs/num/latest/num/trait.FromPrimitive.html
+
+Generic register abstraction
+----------------------------
+
+Work out how register constants and structures can be automatically generated
+through generalized macros.
+
+Example:
+
+.. code-block:: rust
+
+ register!(BOOT0, 0x0, u32, pci::Bar<SIZE>, Fields [
+ MINOR_REVISION(3:0, RO),
+ MAJOR_REVISION(7:4, RO),
+ REVISION(7:0, RO), // Virtual register combining major and minor rev.
+ ])
+
+This could expand to something like:
+
+.. code-block:: rust
+
+ const BOOT0_OFFSET: usize = 0x00000000;
+ const BOOT0_MINOR_REVISION_SHIFT: u8 = 0;
+ const BOOT0_MINOR_REVISION_MASK: u32 = 0x0000000f;
+ const BOOT0_MAJOR_REVISION_SHIFT: u8 = 4;
+ const BOOT0_MAJOR_REVISION_MASK: u32 = 0x000000f0;
+ const BOOT0_REVISION_SHIFT: u8 = BOOT0_MINOR_REVISION_SHIFT;
+ const BOOT0_REVISION_MASK: u32 = BOOT0_MINOR_REVISION_MASK |
BOOT0_MAJOR_REVISION_MASK;
+
+ struct Boot0(u32);
+
+ impl Boot0 {
+ #[inline]
+ fn read(bar: &RevocableGuard<'_, pci::Bar<SIZE>>) ->
Self {
+ Self(bar.readl(BOOT0_OFFSET))
+ }
+
+ #[inline]
+ fn minor_revision(&self) -> u32 {
+ (self.0 & BOOT0_MINOR_REVISION_MASK) >>
BOOT0_MINOR_REVISION_SHIFT
+ }
+
+ #[inline]
+ fn major_revision(&self) -> u32 {
+ (self.0 & BOOT0_MAJOR_REVISION_MASK) >>
BOOT0_MAJOR_REVISION_SHIFT
+ }
+
+ #[inline]
+ fn revision(&self) -> u32 {
+ (self.0 & BOOT0_REVISION_MASK) >> BOOT0_REVISION_SHIFT
+ }
+ }
+
+Usage:
+
+.. code-block:: rust
+
+ let bar = bar.try_access().ok_or(ENXIO)?;
+
+ let boot0 = Boot0::read(&bar);
+ pr_info!("Revision: {}\n", boot0.revision());
+
+| Complexity: Advanced
+
+Delay / Sleep abstractions
+--------------------------
+
+Rust abstractions for the kernel's delay() and sleep() functions.
+
+There is some ongoing work from FUJITA Tomonori [1], which has not seen any
updates
+since Oct. 24.
+
+| Complexity: Beginner
+| Link: https://lore.kernel.org/netdev/20241001112512.4861-2-fujita.tomonori at
gmail.com/ [1]
+
+IRQ abstractions
+----------------
+
+Rust abstractions for IRQ handling.
+
+There is active ongoing work from Daniel Almeida [1] for the "core"
abstractions
+to request IRQs.
+
+Besides optional review and testing work, the required ``pci::Device`` code
+around those core abstractions needs to be worked out.
+
+| Complexity: Intermediate
+| Link: https://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida at
collabora.com/ [1]
+| Contact: Daniel Almeida
+
+Page abstraction for foreign pages
+----------------------------------
+
+Rust abstractions for pages not created by the Rust page abstraction without
+direct ownership.
+
+There is active onging work from Abdiel Janulgue [1].
+
+| Complexity: Advanced
+| Link:
https://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue at
gmail.com/ [1]
+
+Scatterlist / sg_table abstractions
+-----------------------------------
+
+Rust abstractions for scatterlist / sg_table.
+
+There is preceding work from Abdiel Janulgue, which hasn't made it to the
+mailing list yet.
+
+| Complexity: Intermediate
+| Contact: Abdiel Janulgue
+
+ELF utils
+---------
+
+Rust implementation of ELF header representation to retrieve section header
+tables, names, and data from an ELF-formatted images.
+
+There is preceding work from Abdiel Janulgue, which hasn't made it to the
+mailing list yet.
+
+| Complexity: Beginner
+| Contact: Abdiel Janulgue
+
+PCI MISC APIs
+-------------
+
+Extend the existing PCI device / driver abstractions by SR-IOV, config space,
+capability, MSI API abstractions.
+
+| Complexity: Beginner
+
+Auxiliary bus abstractions
+--------------------------
+
+Rust abstraction for the auxiliary bus APIs.
+
+This is needed to connect nova-core to the nova-drm driver.
+
+| Complexity: Intermediate
+
+Debugfs abstractions
+--------------------
+
+Rust abstraction for debugfs APIs.
+
+| Reference: Export GSP log buffers
+| Complexity: Intermediate
+
+Vec extensions
+--------------
+
+Implement ``Vec::truncate`` and ``Vec::resize``.
+
+Currently this is used for some experimental code to parse the vBIOS.
+
+| Reference vBIOS support
+| Complexity: Beginner
+
+GPU (general)
+============+
+Parse firmware headers
+----------------------
+
+Parse ELF headers from the firmware files loaded from the filesystem.
+
+| Reference: ELF utils
+| Complexity: Beginner
+| Contact: Abdiel Janulgue
+
+Build radix3 page table
+-----------------------
+
+Build the radix3 page table to map the firmware.
+
+| Complexity: Intermediate
+| Contact: Abdiel Janulgue
+
+vBIOS support
+-------------
+
+Parse the vBIOS and probe the structures required for driver initialization.
+
+| Contact: Dave Airlie
+| Reference: Vec extensions
+| Complexity: Intermediate
+
+Initial Devinit support
+-----------------------
+
+Implement BIOS Device Initialization, i.e. memory sizing, waiting, PLL
+configuration.
+
+| Contact: Dave Airlie
+| Complexity: Beginner
+
+Boot Falcon controller
+----------------------
+
+Infrastructure to load and execute falcon (sec2) firmware images; handle the
+GSP falcon processor and fwsec loading.
+
+| Complexity: Advanced
+| Contact: Dave Airlie
+
+GPU Timer support
+-----------------
+
+Support for the GPU's internal timer peripheral.
+
+| Complexity: Beginner
+| Contact: Dave Airlie
+
+MMU / PT management
+-------------------
+
+Work out the architecture for MMU / page table management.
+
+We need to consider that nova-drm will need rather fine-grained control,
+especially in terms of locking, in order to be able to implement asynchronous
+Vulkan queues.
+
+While generally sharing the corresponding code is desirable, it needs to be
+evaluated how (and if at all) sharing the corresponding code is expedient.
+
+| Complexity: Expert
+
+VRAM memory allocator
+---------------------
+
+Investigate options for a VRAM memory allocator.
+
+Some possible options:
+ - Rust abstractions for
+ - RB tree (interval tree) / drm_mm
+ - maple_tree
+ - native Rust collections
+
+| Complexity: Advanced
+
+Instance Memory
+---------------
+
+Implement support for instmem (bar2) used to store page tables.
+
+| Complexity: Intermediate
+| Contact: Dave Airlie
+
+GPU System Processor (GSP)
+=========================+
+Export GSP log buffers
+----------------------
+
+Recent patches from Timur Tabi [1] added support to expose GSP-RM log buffers
+(even after failure to probe the driver) through debugfs.
+
+This is also an interesting feature for nova-core, especially in the early
days.
+
+| Link: https://lore.kernel.org/nouveau/20241030202952.694055-2-ttabi at
nvidia.com/ [1]
+| Reference: Debugfs abstractions
+| Complexity: Intermediate
+
+GSP firmware abstraction
+------------------------
+
+The GSP-RM firmware API is unstable and may incompatibly change from version to
+version, in terms of data structures and semantics.
+
+This problem is one of the big motivations for using Rust for nova-core, since
+it turns out that Rust's procedural macro feature provides a rather elegant
way
+to address this issue:
+
+1. generate Rust structures from the C headers in a separate namespace per
version
+2. build abstraction structures (within a generic namespace) that implement the
+ firmware interfaces; annotate the differences in implementation with version
+ identifiers
+3. use a procedural macro to generate the actual per version implementation out
+ of this abstraction
+4. instantiate the correct version type one on runtime (can be sure that all
+ have the same interface because it's defined by a common trait)
+
+There is a PoC implementation of this pattern, in the context of the nova-core
+PoC driver.
+
+This task aims at refining the feature and ideally generalize it, to be usable
+by other drivers as well.
+
+| Complexity: Expert
+
+GSP message queue
+-----------------
+
+Implement low level GSP message queue (command, status) for communication
+between the kernel driver and GSP.
+
+| Complexity: Advanced
+| Contact: Dave Airlie
+
+Bootstrap GSP
+-------------
+
+Call the boot firmware to boot the GSP processor; execute initial control
+messages.
+
+| Complexity: Intermediate
+| Contact: Dave Airlie
+
+Client / Device APIs
+--------------------
+
+Implement the GSP message interface for client / device allocation and the
+corresponding client and device allocation APIs.
+
+| Complexity: Intermediate
+| Contact: Dave Airlie
+
+Bar PDE handling
+----------------
+
+Synchronize page table handling for BARs between the kernel driver and GSP.
+
+| Complexity: Beginner
+| Contact: Dave Airlie
+
+FIFO engine
+-----------
+
+Implement support for the FIFO engine, i.e. the corresponding GSP message
+interface and provide an API for chid allocation and channel handling.
+
+| Complexity: Advanced
+| Contact: Dave Airlie
+
+GR engine
+---------
+
+Implement support for the graphics engine, i.e. the corresponding GSP message
+interface and provide an API for (golden) context creation and promotion.
+
+| Complexity: Advanced
+| Contact: Dave Airlie
+
+CE engine
+---------
+
+Implement support for the copy engine, i.e. the corresponding GSP message
+interface.
+
+| Complexity: Intermediate
+| Contact: Dave Airlie
+
+VFN IRQ controller
+------------------
+
+Support for the VFN interrupt controller.
+
+| Complexity: Intermediate
+| Contact: Dave Airlie
+
+External APIs
+============+
+nova-core base API
+------------------
+
+Work out the common pieces of the API to connect 2nd level drivers, i.e. vGPU
+manager and nova-drm.
+
+| Complexity: Advanced
+
+vGPU manager API
+----------------
+
+Work out the API parts required by the vGPU manager, which are not covered by
+the base API.
+
+| Complexity: Advanced
+
+nova-core C API
+---------------
+
+Implement a C wrapper for the APIs required by the vGPU manager driver.
+
+| Complexity: Intermediate
+
+Testing
+======+
+CI pipeline
+-----------
+
+Investigate option for continuous integration testing.
+
+This can go from as simple as running KUnit tests over running (graphics) CTS
to
+booting up (multiple) guest VMs to test VFIO use-cases.
+
+It might also be worth to consider the introduction of a new test suite
directly
+sitting on top of the uAPI for more targeted testing and debugging. There may
be
+options for collaboration / shared code with the Mesa project.
+
+| Complexity: Advanced
diff --git a/Documentation/gpu/nova/guidelines.rst
b/Documentation/gpu/nova/guidelines.rst
new file mode 100644
index 000000000000..28a959f51c2c
--- /dev/null
+++ b/Documentation/gpu/nova/guidelines.rst
@@ -0,0 +1,73 @@
+.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+=========+Guidelines
+=========+
+This document describes the general project guidelines that apply to nova-core
+and nova-drm.
+
+Language
+=======+
+The Nova project uses the Rust programming language. In this context, the
+following rules apply.
+
+- Unless technically necessary otherwise (e.g. uAPI), any driver code is
written
+ in Rust.
+
+- Direct FFI calls to C kernel APIs must be avoided; instead C kernel APIs
+ should be accessed through shared Rust abstractions.
+
+- Unless technically necessary, unsafe Rust code must be avoided. In case of
+ technical necessity, unsafe code should be isolated in a separate component
+ providing a safe API for other driver code to use.
+
+Style
+-----
+
+All rules of the Rust for Linux project as documented in
+:doc:`../../rust/coding-guidelines` apply. Additionally, the following rules
+apply.
+
+- Code must be formatted with the ``rustfmt`` make target.
+
+- Code submitted for inclusion into the Nova driver project must pass the Rust
+ linter, which can be enabled with ``CLIPPY=1``.
+
+Documentation
+============+
+The availability of proper documentation is essential in terms of scalability,
+accessability for new contributors and maintainability of a project in general,
+but especially for a driver running as complex hardware as Nova is targeting.
+
+Hence, adding documentation of any kind is very much encouraged by the project.
+
+Besides that, there are some minimum requirements.
+
+- Every non-private structure needs at least a brief doc comment explaining the
+ semantical sense of the structure, as well as potential locking and lifetime
+ requirements. It is encouraged to have the same minimum documentation for
+ non-trivial private structures.
+
+- uAPIs must be fully documented with kernel-doc comments; additionally, the
+ semantical behavior must be explained including potential special or corner
+ cases.
+
+- The APIs connecting the 1st level driver (nova-core) with 2nd level drivers
+ must be fully documented. This includes doc comments, potential locking and
+ lifetime requirements, as well as example code if applicable.
+
+- Abbreviations must be explained when introduced; terminology must be uniquely
+ defined.
+
+- Register addresses, layouts, shift values and masks must be defined properly;
+ unless obvious, the semantical sense must be documented. This only applies if
+ the author is able to obtain the corresponding information.
+
+Acceptance Criteria
+==================+
+- Patches must only be applied if reviewed by at least one other person on the
+ mailing list; this also applies for maintainers.
diff --git a/Documentation/gpu/nova/index.rst b/Documentation/gpu/nova/index.rst
new file mode 100644
index 000000000000..2701b3f4af35
--- /dev/null
+++ b/Documentation/gpu/nova/index.rst
@@ -0,0 +1,30 @@
+.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+======================+nova NVIDIA GPU drivers
+======================+
+The nova driver project consists out of two separate drivers nova-core and
+nova-drm and intends to supersede the nouveau driver for NVIDIA GPUs based on
+the GPU System Processor (GSP).
+
+The following documents apply to both nova-core and nova-drm.
+
+.. toctree::
+ :titlesonly:
+
+ guidelines
+
+nova-core
+========+
+The nova-core driver is the core driver for NVIDIA GPUs based on GSP.
nova-core,
+as the 1st level driver, provides an abstraction around the GPUs hard- and
+firmware interfaces providing a common base for 2nd level drivers, such as the
+vGPU manager VFIO driver and the nova-drm driver.
+
+.. toctree::
+ :titlesonly:
+
+ core/guidelines
+ core/todo
diff --git a/MAINTAINERS b/MAINTAINERS
index f7ddca7de0ef..07455c945834 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7454,6 +7454,7 @@ Q: https://patchwork.freedesktop.org/project/nouveau/
B: https://gitlab.freedesktop.org/drm/nova/-/issues
C: irc://irc.oftc.net/nouveau
T: git https://gitlab.freedesktop.org/drm/nova.git nova-next
+F: Documentation/gpu/nova/
F: drivers/gpu/nova-core/
DRM DRIVER FOR OLIMEX LCD-OLINUXINO PANELS
--
2.48.1
Alexandre Courbot
2025-Feb-06 14:05 UTC
[PATCH v2 1/2] gpu: nova-core: add initial driver stub
Hi Danilo, Here are few comments - or maybe I should say nits, as they are really minor. Note that all my experience in Rust is from user-space, so feel free to ignore anything that does not make sense in the context of the kernel or is too pedantic. On Wed Feb 5, 2025 at 4:03 AM JST, Danilo Krummrich wrote:> Add the initial nova-core driver stub. > > nova-core is intended to serve as a common base for nova-drm (the > corresponding DRM driver) and the vGPU manager VFIO driver, serving as a > hard- and firmware abstraction layer for GSP-based NVIDIA GPUs. > > The Nova project, including nova-core and nova-drm, in the long term, > is intended to serve as the successor of Nouveau for all GSP-based GPUs. > > The motivation for both, starting a successor project for Nouveau and > doing so using the Rust programming language, is documented in detail > through a previous post on the mailing list [1], an LWN article [2] and a > talk from LPC '24. > > In order to avoid the chicken and egg problem to require a user to > upstream Rust abstractions, but at the same time require the Rust > abstractions to implement the driver, nova-core kicks off as a driver > stub and is subsequently developed upstream. > > Link: https://lore.kernel.org/dri-devel/Zfsj0_tb-0-tNrJy at cassiopeiae/T/#u [1] > Link: https://lwn.net/Articles/990736/ [2] > Link: https://youtu.be/3Igmx28B3BQ?si=sBdSEer4tAPKGpOs [3] > Signed-off-by: Danilo Krummrich <dakr at kernel.org> > --- > Changes in v2: > - Fix module name in Kconfig description. (John) > - Expand Kconfig description a bit. (John) > - Expand name for PCI BAR0 region. > - Do not store / print boot0 raw register value. (John) > - Rename CardType to Architecture, rename enum names to represent the > architecture name and adjust enum values according to the register > definition. (John) > - Add an abstraction for register accesses. > - Print chipset, architecture and revision. > - Load bootloader firmware. (Timur) > ---<snip>> diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs > new file mode 100644 > index 000000000000..be260a8ffe46 > --- /dev/null > +++ b/drivers/gpu/nova-core/gpu.rs > @@ -0,0 +1,187 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +use kernel::{ > + device, devres::Devres, error::code::*, firmware, fmt, pci, prelude::*, str::CString, > +}; > + > +use crate::driver::Bar0; > +use crate::regs; > +use core::fmt; > + > +/// Enum representation of the GPU chipset. > +#[derive(fmt::Debug)]I suspect you will eventually want to also derive Copy and Clone, as well as PartialEq and Eq (so the assigned values can be used), but it's of course fine to postpone this until we actually need them. Note that the usage made of Debug suggests that you actually want Display - but I understand that implementing Display would be more cumbersome.> +pub(crate) enum Chipset { > + TU102 = 0x162, > + TU104 = 0x164, > + TU106 = 0x166, > + TU117 = 0x167, > + TU116 = 0x168, > + GA102 = 0x172, > + GA103 = 0x173, > + GA104 = 0x174, > + GA106 = 0x176, > + GA107 = 0x177, > + AD102 = 0x192, > + AD103 = 0x193, > + AD104 = 0x194, > + AD106 = 0x196, > + AD107 = 0x197, > +} > + > +/// Enum representation of the GPU generation. > +#[derive(fmt::Debug)] > +pub(crate) enum Architecture { > + Turing = 0x16, > + Ampere = 0x17, > + Ada = 0x19, > +} > + > +pub(crate) struct Revision { > + major: u8, > + minor: u8, > +} > + > +/// Structure holding the metadata of the GPU. > +pub(crate) struct Spec { > + chipset: Chipset, > + arch: Architecture, > + /// The revision of the chipset. > + revision: Revision, > +} > + > +/// Structure encapsulating the firmware blobs required for the GPU to operate. > +#[allow(dead_code)] > +pub(crate) struct Firmware { > + booter_load: firmware::Firmware, > + booter_unload: firmware::Firmware, > + bootloader: firmware::Firmware, > + gsp: firmware::Firmware, > +} > + > +/// Structure holding the resources required to operate the GPU. > +#[allow(dead_code)] > +#[pin_data] > +pub(crate) struct Gpu { > + spec: Spec, > + /// MMIO mapping of PCI BAR 0 > + bar: Devres<Bar0>, > + fw: Firmware, > +} > + > +// TODO replace with something like derive(FromPrimitive) > +impl Chipset { > + fn from_u32(value: u32) -> Option<Chipset> { > + match value { > + 0x162 => Some(Chipset::TU102), > + 0x164 => Some(Chipset::TU104), > + 0x166 => Some(Chipset::TU106), > + 0x167 => Some(Chipset::TU117), > + 0x168 => Some(Chipset::TU116), > + 0x172 => Some(Chipset::GA102), > + 0x173 => Some(Chipset::GA103), > + 0x174 => Some(Chipset::GA104), > + 0x176 => Some(Chipset::GA106), > + 0x177 => Some(Chipset::GA107), > + 0x192 => Some(Chipset::AD102), > + 0x193 => Some(Chipset::AD103), > + 0x194 => Some(Chipset::AD104), > + 0x196 => Some(Chipset::AD106), > + 0x197 => Some(Chipset::AD107), > + _ => None, > + } > + } > +}Shouldn't this be an implementation of TryFrom<u32>? By doing so you can return ENODEV as the error and simplify the caller code below.> + > +// TODO: > +// - replace with something like derive(FromPrimitive) > +// - consider to store within Chipset, if arbitrary_enum_discriminant becomes stable > +impl Architecture { > + fn from_u32(value: u32) -> Option<Architecture> { > + match value { > + 0x16 => Some(Architecture::Turing), > + 0x17 => Some(Architecture::Ampere), > + 0x19 => Some(Architecture::Ada), > + _ => None, > + } > + } > +} > + > +impl Revision { > + fn new(major: u8, minor: u8) -> Self { > + Self { major, minor } > + }Suggestion: add a version that takes a Boot0 as argument and call the right methods directly in the method instead of relying on the caller to do that for us, e.g: fn from_boot0(boot0: ®s::Boot0) -> Self { Self::new(boot0.major_rev(), boot0.minor_rev()) } Then new() can also be removed if Boot0 is the only sensible source of Revision. (I'd argue that Boot0 should also implement Copy, that way this method can take it by value directly)> +} > + > +impl fmt::Display for Revision { > + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { > + write!(f, "{:x}.{:x}", self.major, self.minor) > + } > +} > + > +impl Spec { > + fn new(bar: &Devres<Bar0>) -> Result<Spec> { > + let bar = bar.try_access().ok_or(ENXIO)?; > + let boot0 = regs::Boot0::read(&bar); > + > + let Some(chipset) = Chipset::from_u32(boot0.chipset()) else { > + return Err(ENODEV); > + }; > + > + let Some(arch) = Architecture::from_u32(boot0.arch()) else { > + return Err(ENODEV); > + };Technically the Architecture is already known if the Chipset has been built successfully, so there should be no need to build it again (and test for a failure that cannot happen at this point). Since the architecture information is already embedded in Chipset, maybe we can have an arch() method there? Something like: impl Chipset { pub(crate) fn arch(self) -> Architecture { match self as u32 & !0xf { 0x160 => Architecture::Turing, 0x170 => Architecture::Ampere, 0x190 => Architecture::Ada, _ => unreachable!(), } } } This would also enable us to remove Architecture::from_u32() and Spec::arch, which is redundant with Spec::chipset anyway. A better (but more verbose) implementation of Chipset::arch() might be to match every possible variant, so we get a build error if we forget to handle a new chipset instead of hitting the unreachable!() at runtime...> + > + let revision = Revision::new(boot0.major_rev(), boot0.minor_rev()); > + > + Ok(Self { > + arch, > + chipset, > + revision, > + }) > + } > +} > + > +impl Firmware { > + fn new(dev: &device::Device, spec: &Spec, ver: &str) -> Result<Firmware> { > + let mut chip_name = CString::try_from_fmt(fmt!("{:?}", spec.chipset))?; > + chip_name.make_ascii_lowercase(); > + > + let fw_booter_load_path > + CString::try_from_fmt(fmt!("nvidia/{}/gsp/booter_load-{}.bin", &*chip_name, ver))?; > + let fw_booter_unload_path > + CString::try_from_fmt(fmt!("nvidia/{}/gsp/booter_unload-{}.bin", &*chip_name, ver))?; > + let fw_bootloader_path > + CString::try_from_fmt(fmt!("nvidia/{}/gsp/bootloader-{}.bin", &*chip_name, ver))?; > + let fw_gsp_path > + CString::try_from_fmt(fmt!("nvidia/{}/gsp/gsp-{}.bin", &*chip_name, ver))?; > + > + let booter_load = firmware::Firmware::request(&fw_booter_load_path, dev)?; > + let booter_unload = firmware::Firmware::request(&fw_booter_unload_path, dev)?; > + let bootloader = firmware::Firmware::request(&fw_bootloader_path, dev)?; > + let gsp = firmware::Firmware::request(&fw_gsp_path, dev)?; > + > + Ok(Firmware { > + booter_load, > + booter_unload, > + bootloader, > + gsp, > + })This looks like a good opportunity to use a closure and avoid repeating the code: let request_fw = |type_| { CString::try_from_fmt(fmt!("nvidia/{}/gsp/{}-{}.bin", type_, &*chip_name, ver)) .and_then(|path| firmware::Firmware::request(&path, dev)) }; It is also short enough that you can directly invoke it when building the Firmware object, without using temporary variables: Ok(Firmware { booter_load: request_fw("booter_load")?, booter_unload: request_fw("booter_unload")?, bootloader: request_fw("bootloader")?, gsp: request_fw("gsp")?, }) IMHO this has the benefit of being more concise and keeping related operations closer. Thanks! Alex.
Danilo Krummrich
2025-Feb-06 14:49 UTC
[PATCH v2 1/2] gpu: nova-core: add initial driver stub
Hi Alexandre, On Thu, Feb 06, 2025 at 11:05:37PM +0900, Alexandre Courbot wrote:> > + > > +/// Enum representation of the GPU chipset. > > +#[derive(fmt::Debug)] > > I suspect you will eventually want to also derive Copy and Clone, as > well as PartialEq and Eq (so the assigned values can be used), but it's > of course fine to postpone this until we actually need them.Indeed, the idea is to add it as needed.> > Note that the usage made of Debug suggests that you actually want > Display - but I understand that implementing Display would be more > cumbersome. > > > + > > +// TODO replace with something like derive(FromPrimitive) > > +impl Chipset { > > + fn from_u32(value: u32) -> Option<Chipset> { > > + match value { > > + 0x162 => Some(Chipset::TU102), > > + 0x164 => Some(Chipset::TU104), > > + 0x166 => Some(Chipset::TU106), > > + 0x167 => Some(Chipset::TU117), > > + 0x168 => Some(Chipset::TU116), > > + 0x172 => Some(Chipset::GA102), > > + 0x173 => Some(Chipset::GA103), > > + 0x174 => Some(Chipset::GA104), > > + 0x176 => Some(Chipset::GA106), > > + 0x177 => Some(Chipset::GA107), > > + 0x192 => Some(Chipset::AD102), > > + 0x193 => Some(Chipset::AD103), > > + 0x194 => Some(Chipset::AD104), > > + 0x196 => Some(Chipset::AD106), > > + 0x197 => Some(Chipset::AD107), > > + _ => None, > > + } > > + } > > +} > > Shouldn't this be an implementation of TryFrom<u32>? By doing so you can > return ENODEV as the error and simplify the caller code below.Yes, it should be. I wanted to change that, but forgot about it. Thanks for the reminder. But ultimately, as the comment says, I'd like to have some kind of FromPrimitive implementation for that.> > > + > > +// TODO: > > +// - replace with something like derive(FromPrimitive) > > +// - consider to store within Chipset, if arbitrary_enum_discriminant becomes stable > > +impl Architecture { > > + fn from_u32(value: u32) -> Option<Architecture> { > > + match value { > > + 0x16 => Some(Architecture::Turing), > > + 0x17 => Some(Architecture::Ampere), > > + 0x19 => Some(Architecture::Ada), > > + _ => None, > > + } > > + } > > +} > > + > > +impl Revision { > > + fn new(major: u8, minor: u8) -> Self { > > + Self { major, minor } > > + } > > Suggestion: add a version that takes a Boot0 as argument and call the > right methods directly in the method instead of relying on the caller to > do that for us, e.g: > > fn from_boot0(boot0: ®s::Boot0) -> Self { > Self::new(boot0.major_rev(), boot0.minor_rev()) > } > > > Then new() can also be removed if Boot0 is the only sensible source of > Revision.That's a good suggestion, I'll pick that up.> > (I'd argue that Boot0 should also implement Copy, that way this method > can take it by value directly) > > > +} > > + > > +impl fmt::Display for Revision { > > + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { > > + write!(f, "{:x}.{:x}", self.major, self.minor) > > + } > > +} > > + > > +impl Spec { > > + fn new(bar: &Devres<Bar0>) -> Result<Spec> { > > + let bar = bar.try_access().ok_or(ENXIO)?; > > + let boot0 = regs::Boot0::read(&bar); > > + > > + let Some(chipset) = Chipset::from_u32(boot0.chipset()) else { > > + return Err(ENODEV); > > + }; > > + > > + let Some(arch) = Architecture::from_u32(boot0.arch()) else { > > + return Err(ENODEV); > > + }; > > Technically the Architecture is already known if the Chipset has been > built successfully, so there should be no need to build it again (and > test for a failure that cannot happen at this point). > > Since the architecture information is already embedded in Chipset, maybe > we can have an arch() method there? > > Something like: > > impl Chipset { > pub(crate) fn arch(self) -> Architecture { > match self as u32 & !0xf { > 0x160 => Architecture::Turing, > 0x170 => Architecture::Ampere, > 0x190 => Architecture::Ada, > _ => unreachable!(), > } > } > }I thought about this, which is also why the comment above says: "consider to store within Chipset, if arbitrary_enum_discriminant becomes stable". I did not go with what you suggest because it leaves us with either Chipset::arch() returning a Result, which is annoying, or with Chipset::arch() being able to panic the kernel, which I'd dislike even more. There's also a third option, which would be to have some kind of unknown architecture, which we could catch later on, but that's just a worse variation of returning a Result. Another reason was that I did not want to encode register specific masks into the Chipset type.> > > This would also enable us to remove Architecture::from_u32() and > Spec::arch, which is redundant with Spec::chipset anyway. > > A better (but more verbose) implementation of Chipset::arch() might be > to match every possible variant, so we get a build error if we forget to > handle a new chipset instead of hitting the unreachable!() at runtime...I think that would indeed be a reasonable option.> > > + > > + let revision = Revision::new(boot0.major_rev(), boot0.minor_rev()); > > + > > + Ok(Self { > > + arch, > > + chipset, > > + revision, > > + }) > > + } > > +} > > + > > +impl Firmware { > > + fn new(dev: &device::Device, spec: &Spec, ver: &str) -> Result<Firmware> { > > + let mut chip_name = CString::try_from_fmt(fmt!("{:?}", spec.chipset))?; > > + chip_name.make_ascii_lowercase(); > > + > > + let fw_booter_load_path > > + CString::try_from_fmt(fmt!("nvidia/{}/gsp/booter_load-{}.bin", &*chip_name, ver))?; > > + let fw_booter_unload_path > > + CString::try_from_fmt(fmt!("nvidia/{}/gsp/booter_unload-{}.bin", &*chip_name, ver))?; > > + let fw_bootloader_path > > + CString::try_from_fmt(fmt!("nvidia/{}/gsp/bootloader-{}.bin", &*chip_name, ver))?; > > + let fw_gsp_path > > + CString::try_from_fmt(fmt!("nvidia/{}/gsp/gsp-{}.bin", &*chip_name, ver))?; > > + > > + let booter_load = firmware::Firmware::request(&fw_booter_load_path, dev)?; > > + let booter_unload = firmware::Firmware::request(&fw_booter_unload_path, dev)?; > > + let bootloader = firmware::Firmware::request(&fw_bootloader_path, dev)?; > > + let gsp = firmware::Firmware::request(&fw_gsp_path, dev)?; > > + > > + Ok(Firmware { > > + booter_load, > > + booter_unload, > > + bootloader, > > + gsp, > > + }) > > This looks like a good opportunity to use a closure and avoid > repeating the code: > > let request_fw = |type_| { > CString::try_from_fmt(fmt!("nvidia/{}/gsp/{}-{}.bin", type_, &*chip_name, ver)) > .and_then(|path| firmware::Firmware::request(&path, dev)) > }; > > It is also short enough that you can directly invoke it when building > the Firmware object, without using temporary variables: > > Ok(Firmware { > booter_load: request_fw("booter_load")?, > booter_unload: request_fw("booter_unload")?, > bootloader: request_fw("bootloader")?, > gsp: request_fw("gsp")?, > }) > > IMHO this has the benefit of being more concise and keeping related > operations closer.I agree, that's pretty clean.> > Thanks! > Alex. >