Yang Yingliang
2022-Nov-18 09:17 UTC
[Nouveau] [PATCH] drm/nouveau/kms/nv04: fix pci device refcount leak
As comment of pci_get_domain_bus_and_slot() says, it returns
a pci device with refcount increment, when finish using it,
the caller must decrement the reference count by calling
pci_dev_put().
In nv04_update_arb() and nouveau_hw_get_clock(), after using
pci_dev_put() is called to avoid refcount leak.
Fixes: 6ee738610f41 ("drm/nouveau: Add DRM driver for NVIDIA GPUs")
Signed-off-by: Yang Yingliang <yangyingliang at huawei.com>
---
drivers/gpu/drm/nouveau/dispnv04/arb.c | 6 ++++--
drivers/gpu/drm/nouveau/dispnv04/hw.c | 13 +++++++++----
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv04/arb.c
b/drivers/gpu/drm/nouveau/dispnv04/arb.c
index 1d3542d6006b..697e67fb21d3 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/arb.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/arb.c
@@ -209,11 +209,13 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
sim_data.two_heads = nv_two_heads(dev);
if ((pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
(pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
+ struct pci_dev *pdev;
uint32_t type;
int domain = pci_domain_nr(pdev->bus);
- pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1),
- 0x7c, &type);
+ pdev = pci_get_domain_bus_and_slot(domain, 0, 1);
+ pci_read_config_dword(pdev, 0x7c, &type);
+ pci_dev_put(pdev);
sim_data.memory_type = (type >> 12) & 1;
sim_data.memory_width = 64;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c
b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index f7d35657aa64..52e3999225d5 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -216,6 +216,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum
nvbios_pll_type plltype)
{
struct pci_dev *pdev = to_pci_dev(dev->dev);
struct nvkm_pll_vals pllvals;
+ struct pci_dev *tmp_pdev;
int ret;
int domain;
@@ -224,8 +225,10 @@ nouveau_hw_get_clock(struct drm_device *dev, enum
nvbios_pll_type plltype)
if (plltype == PLL_MEMORY &&
(pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
uint32_t mpllP;
- pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
- 0x6c, &mpllP);
+
+ tmp_pdev = pci_get_domain_bus_and_slot(domain, 0, 3);
+ pci_read_config_dword(tmp_pdev, 0x6c, &mpllP);
+ pci_dev_put(tmp_pdev);
mpllP = (mpllP >> 8) & 0xf;
if (!mpllP)
mpllP = 4;
@@ -236,8 +239,10 @@ nouveau_hw_get_clock(struct drm_device *dev, enum
nvbios_pll_type plltype)
(pdev->device & 0xff0) == CHIPSET_NFORCE2) {
uint32_t clock;
- pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 5),
- 0x4c, &clock);
+ tmp_pdev = pci_get_domain_bus_and_slot(domain, 0, 5);
+ pci_read_config_dword(tmp_pdev, 0x4c, &clock);
+ pci_dev_put(tmp_pdev);
+
return clock / 1000;
}
--
2.25.1