Hi, I think a nice project would be to write an application to figure out those latencies automatically maybe even based on envydis. It could generate latency information based on thread count, register usage, instruction/instruction class, hw unit used. Or even tries to figure out what kind of units exist. Like instructions out of a group which are free to issue/execute after instructions out of another one. I could imagine, that this allone might be a really huge project, but useful for future and past chipsets. On 17 January 2017 10:28:20 p.m. GMT+01:00, Ilia Mirkin <imirkin at alum.mit.edu> wrote:>There's not a lot of information about it. Basically we need 2 >instruction >scheduling passes -- one pre-RA and one post-RA. The prerequisites are >"know how compilers work" and "have a GPU that you can test performance >on". > >I won't beat around the bush - this is a very tough project. Every >attempt >at it so far has basically failed. There are a lot of issues that have >to >be dealt with, like how to properly get the instruction latency >information, and how to apply it while taking ideas like register >pressure >into account. > >You can read up on the nouveau codegen compiler here: >https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/codegen/ > >Cheers, > > -ilia > > >On Tue, Jan 17, 2017 at 8:58 AM, Shailesh Tripathi < >shailesh.tripathi.ece13 at itbhu.ac.in> wrote: > >> Hello, >> I am quite interested in the project "Instruction Scheduler" under >X.org. >> Please tell me where can I find a detailed idea of the project and >how to >> start it. I think I have the given prerequisites. >> >> Regards >> Shailesh Tripathi >> >> >> Shailesh Tripathi >> B.Tech. Part-IV >> Electronics Engineering >> IIT-BHU (Varanasi) >> >> _______________________________________________ >> Nouveau mailing list >> Nouveau at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/nouveau >> >>
Hello, Even I think it would be a very big project for just 3 months, but it would be fun learning and developing this. I feel I have the required skills and would like to learn more for this. I have just one doubt regarding the GPU required for the task. Will a normal NVIDIA GT 740m would be enough or we need better GPUs like Tesla or Quadro? In the latter case how can one proceed in case of its unavailability? Regards Shailesh Shailesh Tripathi B.Tech. Part-III Electronics Engineering IIT-BHU (Varanasi) On Wed, Jan 18, 2017 at 3:48 AM, Karol Herbst <karolherbst at gmail.com> wrote:> Hi, > > I think a nice project would be to write an application to figure out > those latencies automatically maybe even based on envydis. > > It could generate latency information based on thread count, register > usage, instruction/instruction class, hw unit used. Or even tries to figure > out what kind of units exist. Like instructions out of a group which are > free to issue/execute after instructions out of another one. > > I could imagine, that this allone might be a really huge project, but > useful for future and past chipsets. > > On 17 January 2017 10:28:20 p.m. GMT+01:00, Ilia Mirkin < > imirkin at alum.mit.edu> wrote: > >There's not a lot of information about it. Basically we need 2 > >instruction > >scheduling passes -- one pre-RA and one post-RA. The prerequisites are > >"know how compilers work" and "have a GPU that you can test performance > >on". > > > >I won't beat around the bush - this is a very tough project. Every > >attempt > >at it so far has basically failed. There are a lot of issues that have > >to > >be dealt with, like how to properly get the instruction latency > >information, and how to apply it while taking ideas like register > >pressure > >into account. > > > >You can read up on the nouveau codegen compiler here: > >https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/ > drivers/nouveau/codegen/ > > > >Cheers, > > > > -ilia > > > > > >On Tue, Jan 17, 2017 at 8:58 AM, Shailesh Tripathi < > >shailesh.tripathi.ece13 at itbhu.ac.in> wrote: > > > >> Hello, > >> I am quite interested in the project "Instruction Scheduler" under > >X.org. > >> Please tell me where can I find a detailed idea of the project and > >how to > >> start it. I think I have the given prerequisites. > >> > >> Regards > >> Shailesh Tripathi > >> > >> > >> Shailesh Tripathi > >> B.Tech. Part-IV > >> Electronics Engineering > >> IIT-BHU (Varanasi) > >> > >> _______________________________________________ > >> Nouveau mailing list > >> Nouveau at lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/nouveau > >> > >> >-------------- next part -------------- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/nouveau/attachments/20170119/7ee86b60/attachment.html>
On Thu, Jan 19, 2017 at 11:40 AM, Shailesh Tripathi < shailesh.tripathi.ece13 at itbhu.ac.in> wrote:> Hello, > Even I think it would be a very big project for just 3 months, but it > would be fun learning and developing this. I feel I have the required > skills and would like to learn more for this. I have just one doubt > regarding the GPU required for the task. Will a normal NVIDIA GT 740m would > be enough or we need better GPUs like Tesla or Quadro? In the latter case > how can one proceed in case of its unavailability? >Any NVIDIA GPU that's presently supported by nouveau should be sufficient. The GT 740M should be fine, but definitely test it out with nouveau first to make sure that you can get it to work OK. What kind of pre-existing compiler experience do you have? Do you have concrete ideas on tackling this problem? As part of the GSoC application you'll have to come up with a development plan, and find a mentor (who ostensibly has to believe that you'll have a good chance of completing such a project). Cheers, -ilia -------------- next part -------------- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/nouveau/attachments/20170119/d984a8e0/attachment.html>