林政宗 via llvm-dev
2021-Aug-10 11:54 UTC
[llvm-dev] How to define subreg relationship in td file?
Hi, there. I met a problem about defining SubReg relationship when defining Registers in td file. The target has a kind of vector register named VR which is of type v4f32. 2 VR makes 1 DVR. 4 VR makes 1 QVR. I have some code like this: ------------------------------------------------------------------------------------------------------ def VRPairs : RegisterTuples<[vsub_0, vsub_1], [(decimate (rotl VRegs, 0), 2), (decimate (rotl VRegs, 1), 2)], []>; def VRQuads : RegisterTuples<[vsub_0, vsub_1, vsub_2, vsub_3], [(decimate (rotl VRegs, 0), 4), (decimate (rotl VRegs, 1), 4), (decimate (rotl VRegs, 2), 4), (decimate (rotl VRegs, 3), 4)], []>; def DVRRegs : RegisterClass<"xxx", [v8f32], 256, (add VRPairs)>; def QVRRegs : RegisterClass<"xxx", [v16f32], 512, (add VRQuads)>; ------------------------------------------------------------------------------------------------------ But also, 2 DVR makes 1 QVR. QVR has two subregs, each of which is 1 DVR. How can I describe the SubReg relationship between DVR and QVR? Could anyone help? Thanks in advance! BR, Jerry -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20210810/2497b222/attachment.html>
Fraser Cormack via llvm-dev
2021-Aug-10 12:15 UTC
[llvm-dev] How to define subreg relationship in td file?
Hi, You can (I'm hesitant to say you "must") model this with extra "fake" (in some sense) physical registers which represent the paired and quadrupled registers. This will also tell the register allocator that allocating VRPair0 will clobber both VR0 *and VR1*, for example. So you have half the number of VRPair registers which each have two VRs as subregisters, then half that again of VRQuad registers which have two VRPairs as subregisters. The subregister properties will apply transitively so your VRQuads will have four VR subregisters using composed subregister indices which LLVM will either automatically infer or you can specify yourself with ComposedSubRegIndex. Take a look at RISCVRegisterInfo.td for inspriation. Each vector V register is paired into VM2 which are in turn paried into VM4s and then into VM8s. Cheers, Fraser On Tue, 2021-08-10 at 19:54 +0800, 林政宗 via llvm-dev wrote:> Hi, there. > > I met a problem about defining SubReg relationship when defining > Registers in td file. > The target has a kind of vector register named VR which is of type > v4f32. > 2 VR makes 1 DVR. 4 VR makes 1 QVR. > I have some code like this: > ------------------------------------------------------------------- > ----------------------------------- > def VRPairs : RegisterTuples<[vsub_0, vsub_1], > [(decimate (rotl VRegs, 0), 2), > (decimate (rotl VRegs, 1), 2)], > []>; > > def VRQuads : RegisterTuples<[vsub_0, vsub_1, vsub_2, vsub_3], > [(decimate (rotl VRegs, 0), 4), > (decimate (rotl VRegs, 1), 4), > (decimate (rotl VRegs, 2), 4), > (decimate (rotl VRegs, 3), 4)], > []>; > def DVRRegs : RegisterClass<"xxx", [v8f32], 256, (add VRPairs)>; > > def QVRRegs : RegisterClass<"xxx", [v16f32], 512, (add VRQuads)>; > ------------------------------------------------------------------- > ----------------------------------- > But also, 2 DVR makes 1 QVR. QVR has two subregs, each of which is 1 > DVR. > How can I describe the SubReg relationship between DVR and QVR? > Could anyone help? Thanks in advance! > > > BR, > Jerry > > > > > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >