llvm dev - Aug 2021 - Help request about ReplaceNode in ISelDAGToDAG

Hello,


I would like to make some DAG transform in RISCV's ISelDAGToDAG, but I find
the ReplaceNode() requests


the new Node to be a MachineNode( usually created be curDAG->getMachineNode
with the opcode set to RISCV::xxxx).


Can I just pass it a SDNode (with opcode set to anoher ISD::xxx, not RISCV::xxx)
? It seems LLVM will crash.


Because I want to change the opcode to ADD, can I avoid the complexity of
selecting ADDW/ADDI/ADDIW for a machine node in different cases?


Ben Shi

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There isn't really enough information here to understand exactly what you
need, but it almost certainly won't require you to use ReplaceNode.
ISelDAGToDAG is a place where you do instruction selection and instruction
selection needs machine SD nodes by definition - you can't have target
independent nodes after selection. It really sounds like you are interested
in writing a DAGCombine transformation. Of course, it is possible that you
need a specific custom legalization which is a little different, but I will
assume you need a DAG combine as your question sounds the most like a DAG
combine.

The way you would accomplish this is to mark the input node as one for
which you have a DAG combine. You accomplish this using
setTargetDAGCombine(<node>). Looks like RISCV has a handful of nodes for
which they have combines. Then in RISCVTargetLowering::PerformDAGCombine(),
you will add your node to the switch and dispatch to the function that
performs your DAG combine. You can follow the example of ISD::AND in
RISCVISelLowering.cpp which gets combined in performANDCombine().

I hope this helps, but I realize that I may be completely off in terms of
what you are after.

On Sat, Aug 7, 2021 at 12:05 PM Ben Shi via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hello,
>
> I would like to make some DAG transform in RISCV's ISelDAGToDAG, but I
> find the ReplaceNode() requests
>
> the new Node to be a MachineNode( usually created be
> curDAG->getMachineNode with the opcode set to RISCV::xxxx).
>
> Can I just pass it a SDNode (with opcode set to anoher ISD::xxx, not
> RISCV::xxx) ? It seems LLVM will crash.
>
> Because I want to change the opcode to ADD, can I avoid the complexity of
> selecting ADDW/ADDI/ADDIW for a machine node in different cases?
>
> Ben Shi
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
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