llvm dev - Mar 2021 - Tablegen backend for emulator core?

On Wed, 17 Mar 2021 at 21:59, John Byrd via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
>
> Howdy llvm-dev,
>
> Low priority question.  This doesn't really meet the requirements for
an RFC, because it's probably merely a half-baked idea at this point.
>
> As I was working with some tablegen internals on an 8-bit processor
backend, it struck me that I would need at some point to write an emulator for
that processor.
>
> And I realized that, although I could write an emulator in the traditional
manner, tablegen already has most of the information it needs to automatically
generate the guts of an emulator.
>
> Tablegen's already generating a disassembler (-gen-disassembler).
>
> At the least, tablegen could be given an additional backend that says,
"given this instruction, do this emulation step."  Such a step could
be pure code copied from the .td files, or it could be compositionally
constructed based on the classes that an object is composed from.
>
> You'd have to write your own code to deal with emulated machine state,
but hey, instruction parsing would be an item off the to-do list.
>
> I would have a hard time believing that this concept is novel.  Has anyone
else taken a crack at this?
Hi John,

Simon Cook (CCed) previously used LLVM MC to help write a simulator
<https://llvm.org/devmtg/2016-01/slides/fosdem16-aapsim.pdf>, which
might be worth taking a look at. Though I understood from your email
that you're imagining relying more heavily on TableGen for generating
the execution loop.

Best,

Alex

> > And I realized that, although I could write an emulator in the
> traditional manner, tablegen already has most of the information it needs
> to automatically generate the guts of an emulator.
>
> > Simon Cook (CCed) previously used LLVM MC to help write a simulator
<
> https://llvm.org/devmtg/2016-01/slides/fosdem16-aapsim.pdf>, which might
> be worth taking a look at. Though I understood from your email that
you're
> imagining relying more heavily on TableGen for generating the execution
> loop.
>
Thank you.  I think Cook understood what I was hinting at, towards the end
of his presentation.  You could build such a simulator by creating a large
switch statement based on MCInst's the way that Cook has done, or you could
theoretically let tablegen create that switch for you.... llvm-tblgen
-gen-simulator was the way he put this idea.  At the least, the concept
maintains tablegen's DRY approach to representing machine instructions.

jwb
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20210321/79a68615/attachment.html>