Paul C. Anagnostopoulos via llvm-dev
2021-Feb-01 23:33 UTC
[llvm-dev] Problem in AMDGPU TableGen files
Yes, I can add a couple of lines of code to tgparser.cpp that will just check the types and complain if they aren't correct. I'll do that on Tuesday/Wednesday on Phabricator.
Craig Topper via llvm-dev
2021-Feb-02 01:28 UTC
[llvm-dev] Problem in AMDGPU TableGen files
Are you also failing on RISCV, I see things that should fail.
For example, RISCVInstrInfoVSDPatterns.td contains
defm "" : VPatUSLoadStoreSDNodes<AddrFI>;
Where AddrFI is a complex pattern, but VPatUSLoadStoreSDNodes is defined
to take a RegisterClass.
multiclass VPatUSLoadStoreSDNodes<RegisterClass reg_rs1> {
~Craig
On Mon, Feb 1, 2021 at 3:33 PM Paul C. Anagnostopoulos via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Yes, I can add a couple of lines of code to tgparser.cpp that will just
> check the types and complain if they aren't correct. I'll do that
on
> Tuesday/Wednesday on Phabricator.
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
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