Zhang via llvm-dev
2020-Dec-31 08:18 UTC
[llvm-dev] "Bits value must be constants" when generating ISel from Tablegen
I had two Instruction class definitions in my InstructionFormat TableGen, as
listed below:
```
class InstRI8<bits<8> opcode,string asm,dag outs,dag ins> :
Instruction{
........
}
class InstRI8222<bits<8> opcode,string asm,dag outs,dag
ins,list<dag> Pat> : Instruction{
........
let Pattern = Pat;
}
```
However later when initializing those two classes, if I use the following format
to initialize the instruction:
```
def X : InstRI8<...>{
let Pattern = [ ...... ];
}
```
I got a error from Tablegen that says "Bits value must be
constants" for this def.
Using the second Instruction Class which models Pattern as the template argument
works perfectly fine
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