Riyaz Puthiyapurayil via llvm-dev
2020-Jun-12 01:31 UTC
[llvm-dev] Why doesn't this `and` get eliminated
define dso_local i32 @f(i32 %0) {
%2 = and i32 %0, 7
%3 = icmp eq i32 %2, 7
%4 = zext i1 %3 to i32
ret i32 %4
}
I thought instcombine would remove it. It doesn't and nothing else does
either. LLVM Version is 10.0.0.
/Riyaz
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Craig Topper via llvm-dev
2020-Jun-12 01:56 UTC
[llvm-dev] Why doesn't this `and` get eliminated
I don't think its legal to remove it. That code is equivalent to asking (%0 mod 8) == 7. Which is true for 7 and 15 and 23, etc. You can't just remove the mod part of that or it would just return true for %0 == 7. ~Craig On Thu, Jun 11, 2020 at 6:31 PM Riyaz Puthiyapurayil via llvm-dev < llvm-dev at lists.llvm.org> wrote:> define dso_local i32 @f(i32 %0) { > > %2 = and i32 %0, 7 > > %3 = icmp eq i32 %2, 7 > > %4 = zext i1 %3 to i32 > > ret i32 %4 > > } > > > > I thought instcombine would remove it. It doesn’t and nothing else does > either. LLVM Version is 10.0.0. > > > > /Riyaz > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200611/22199736/attachment.html>
John Regehr via llvm-dev
2020-Jun-12 05:03 UTC
[llvm-dev] Why doesn't this `and` get eliminated
alive2 agrees with Craig:
----------------------------------------
define i32 @src(i32 %0) {
%1:
%2 = and i32 %0, 7
%3 = icmp eq i32 %2, 7
%4 = zext i1 %3 to i32
ret i32 %4
}
=>
define i32 @tgt(i32 %0) {
%1:
%x3 = icmp eq i32 %0, 7
%x4 = zext i1 %x3 to i32
ret i32 %x4
}
Transformation doesn't verify!
ERROR: Value mismatch
Example:
i32 %0 = #x0000000f (15)
Source:
i32 %2 = #x00000007 (7)
i1 %3 = #x1 (1)
i32 %4 = #x00000001 (1)
Target:
i1 %x3 = #x0 (0)
i32 %x4 = #x00000000 (0)
Source value: #x00000001 (1)
Target value: #x00000000 (0)
Riyaz Puthiyapurayil via llvm-dev
2020-Jun-17 04:36 UTC
[llvm-dev] Why doesn't this `and` get eliminated
Oops! My bad! The code I intended to write was:
define dso_local i32 @f(i3 %0) {
%2 = and i3 %0, 7
%3 = icmp eq i3 %2, 7
%4 = zext i1 %3 to i32
ret i32 %4
}
The `and` does get removed in this case as expected. Thanks for answering the
dumb question. 😊
/Riyaz
From: Craig Topper <craig.topper at gmail.com>
Sent: Thursday, June 11, 2020 6:57 PM
To: Riyaz Puthiyapurayil <riyaz at synopsys.com>
Cc: llvm-dev <llvm-dev at lists.llvm.org>
Subject: Re: [llvm-dev] Why doesn't this `and` get eliminated
I don't think its legal to remove it. That code is equivalent to asking (%0
mod 8) == 7. Which is true for 7 and 15 and 23, etc. You can't just remove
the mod part of that or it would just return true for %0 == 7.
~Craig
On Thu, Jun 11, 2020 at 6:31 PM Riyaz Puthiyapurayil via llvm-dev <llvm-dev
at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote:
define dso_local i32 @f(i32 %0) {
%2 = and i32 %0, 7
%3 = icmp eq i32 %2, 7
%4 = zext i1 %3 to i32
ret i32 %4
}
I thought instcombine would remove it. It doesn’t and nothing else does either.
LLVM Version is 10.0.0.
/Riyaz
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