llvm dev - Dec 2019 - Discuss about the LLVM SW mitigation to Jump Conditional Code Erratum

Hi all,

I'd like to discuss about the LLVM SW mitigation to Jump Conditional Code
Erratum in this mailing thread. The patch was submitted in phabricator
https://reviews.llvm.org/D70157. There were many review comments about its
performance/code size impact, and some suggestions how to make the patches more
generic to apply to other scenarios.

Let's start from the performance/code size/build time impact. Below is the
data we got from the test suite.
LLVM test-suite

Baseline

sw_prefix

hw

hw_sw_prefix


compile_time

0.276

0.282

0.276

0.282

exec_time

286.465

285.017

291.294

287.766

code_size

3.868

3.889

3.868

3.889





LLVM test-suite

Baseline

sw_prefix

hw

hw_sw_prefix


compile_time

1.000

1.021

1.000

1.021

exec_time

1.000

0.995

1.017

1.005

code_size

1.000

1.005

1.000

1.005


Test date:
              2019/11/25

System Configuration:
OS: Red Hat* 8.0 x86_64
Memory: 191 GB
CPUCount: 2
CoreCount: 40
Intel HyperThreading: yes
CPU Model: Intel(R) Xeon(R) Gold 6148 CPU @ 2.40GHz
Microcode w/o hw mitigation: 0x200005e
Microcode with hw mitigation: 0x2000063













  1.  Baseline means the system w/o MCU mitigation and w/o SW mitigation.
  2.  SW_prefix means prefix mitigation is applied to a Non MCU system.
  3.  HW means the MCU mitigation is applied w/o SW mitigation.
  4.  HW+SW means both MCU and prefix mitigations are applied.
  5.  The data in 2nd table is normalized as the ratio vs. baseline. The smaller
the better.
  6.  The test is done on an engineering build plus the SW mitigation patch. It
may be variant from build to build.

The data indicates that there's some performance penalty (1.7%) in HW
mitigation. And it reduced to 0.5% with prefix mitigated. The code size increase
in test suite is about 0.5%. And the compile time increase is about 2%.

More data will follow.

Thanks,
Annita

For more complete information about performance and benchmark results, visit
www.intel.com/benchmarks<http://www.intel.com/benchmarks>.  For specific
information and notices/disclaimers regarding the Jump Conditional Code Erratum,
visit
https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf.






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