llvm dev - Sep 2019 - Maybe a TableGen bug?

Hi,

Here's llvm-tblgen -print-records message:
def LOADbos { // Instruction ABCInst ABCInstMMEMrr
  field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0,
0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4},
roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  string Namespace = "ABC";
  dag OutOperandList = (outs GPR_OUT:$rs1);
  dag InOperandList = (ins SGPR32:$rbase, MGPR_ST:$roffset, uimm2:$rshift);
  string AsmString = "LOAD [$rbase + ( $roffset << $rshift )],
$rs1";
  list<dag> Pattern = [(set i16v:$rs1, (load (add i32:$rbase, (shl (*sext
(i16 (bitconvert i16v:$roffset))*), i32:$rshift))))];
.....
i16v is a new type we added, same as i16, only name differ.

While -gen-dag-isel, hit the following issue:
Value type size is target-dependent. Ask TLI.
UNREACHABLE executed at
/home/nancy/rpp_llvm/rpp_clang/llvm/include/llvm/Support/MachineValueType.h:643!

Is that a TableGen bug?

llvm 8.0.0 version.

-- 
Best Regards,
Yu Rong Tan
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Hi Nancy,

On Fri, 27 Sep 2019 at 03:50, Nancy via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> UNREACHABLE executed at
/home/nancy/rpp_llvm/rpp_clang/llvm/include/llvm/Support/MachineValueType.h:643!
>
> Is that a TableGen bug?
It looks more like you forgot to add your new type to that switch statement.

Cheers.

Tim.

Hi Tim,


On Fri, Sep 27, 2019 at 4:38 PM Tim Northover <t.p.northover at gmail.com>
wrote:
>
> Hi Nancy,
>
> On Fri, 27 Sep 2019 at 03:50, Nancy via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
> > UNREACHABLE executed at
/home/nancy/rpp_llvm/rpp_clang/llvm/include/llvm/Support/MachineValueType.h:643!
> >
> > Is that a TableGen bug?
>
> It looks more like you forgot to add your new type to that switch
statement.
I did add i16v and i32v to switch statement in getSizeInBits().

-- 
Best Regards,
Yu Rong Tan