Hi,
I have a special hardware, it have two different ALU units, use different
registers. It's hard for DAGIsel to map i32 ISD::ADD to different ALU
because LLVM does not aware register class's differ.
def 16rr : ABCInstALU0rr<funct4, 0b0, *OPC_ALU0*,
(outs* GPR_OUT*:$vx), (ins *GPR:*$rs1, *GPR:*
$rs2),
!strconcat(opcodestr,".S16"),
"$rs1, $rs2,
$vx",
[(set i16:$vx, (OpNode i16:$rs1,
i16:$rs2))]>;
def 16rr : ABCInstALU1rr<funct4, 0b0, *OPC_ALU1*,
(outs *SGPR16*:$vx), (ins *SGPR16*:$rs1,
*SGPR16*:$rs2),
!strconcat(opcodestr,".S16"),
"$rs1, $rs2,
$vx",
[(set i16:$vx, (OpNode i16:$rs1,
i16:$rs2))]>;
5 for(i=0; i<loopNum; i++ )
6 a[i+offset] = b;
line 5: i++ have to run on ALU0
line 6: i+offset have to run on ALU1
It's hard for me to add context analysis during DAG because that is
function scope analysis and also hard to change reigster class(Is there any
API for register class update? ).
So I think maybe I should introduce MVT::i16s type and add a pass just
before creating SDNode to complete context analysis and update MVT type to
solve this issue. What's your suggestion?
--
Best Regards,
Yu Rong Tan
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20190916/bf8f377a/attachment.html>