llvm dev - Aug 2019 - GSoC'19 with FOSSi: Supporting 64 bit pointers in RISCV 32 bit LLVM backend

Hello everyone,

I participated in GSoC'19 with The Free and Open Source Silicon Foundation
(FOSSi, https://fossi-foundation.org/) under the mentorship of Prof.
Michael Taylor.
Prof. Taylor's Bespoke Silicon Group is working on the design of the second
version of their RISCV based GPGPU (bjump.org/manycore/). This summer I
worked to add support for 64 bit pointers in RISCV 32 bit backend by adding
custom load and store instruction which can handle 64 bit addresses in
address space 1.
The code is hosted at https://github.com/reSHARMA/RISCV32-GPU I have also
written a small write-up (WIP) about the challenges we faced and all the
approaches we tried for supporting two new instructions in RISCV LLVM
backend.
https://github.com/reSHARMA/RISCV32-GPU/blob/master/GSoCWorkSubmission.md#supporting-64-bit-pointers-in-32-bit-riscv-llvm-backend

We have tested it on small test cases and it worked well, We have halted
the testing until we get some performance result. We are trying to make it
work first through emulation.
We also look forward to support more GPGPU specific instructions in future.

I would thank Prof. Taylor for his vision, Neil Ryan for all the
discussions. I've got lot of help from llvm-dev mailing list especially
Tim, his suggestions were gold. Million thanks to Alex bradbury and the
whole riscv-llvm community for the infinite help, support and bearing me
for last 3 months and for many months coming ahead :)

Many thanks,
Reshabh Sharma
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