llvm dev - Aug 2019 - Can register class effect ISel pattern?

Hi,
Can register class effect Instruction selection prefer in ISel pattern?

Example:
Same LLVM IR add instruction, same data type i32, different asm
instruction, different register class  GPR,  SGPR
if one operator comes from GPR register class, it selects GPR "add"
instruction
if all operators come from SGPR register class, it select SGPR "add"
instruction


-- 
Best Regards,
Yu Rong Tan

Hi Yu,

I don’t think that you can make LLVM to do it for you automatically based on the
tablegen files alone, but you should be able to implement this in
yourTargetDAGToDAGISel::Select function. Check for the ISD::ADD instruction to
come, then replace it by your 'gpr-add', or ‘sgpr-add' instruction
depending on its operands by calling CurDAG->SelectNodeTo.

Joan
> On 1 Aug 2019, at 05:31, Nancy via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> 
> Hi,
> Can register class effect Instruction selection prefer in ISel pattern?
> 
> Example:
> Same LLVM IR add instruction, same data type i32, different asm
> instruction, different register class  GPR,  SGPR
> if one operator comes from GPR register class, it selects GPR
"add" instruction
> if all operators come from SGPR register class, it select SGPR
"add" instruction
> 
> 
> -- 
> Best Regards,
> Yu Rong Tan
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

Hi Nancy,

No, in general register classes haven't been assigned yet when instruction
selection is trying to match the SelectionDAG representation. When you specify a
register class in a pattern you're actually specifying the types that can be
stored in that register class.

GlobalISel is slightly different though. GlobalISel adds a 'register
bank' concept which is available to the instruction selector when it tries
to match. In this case specifying a register class in a pattern specifies the
types that can be stored in the class as well as the bank the class belongs to.
There's another pass called Register Bank Allocator that assigns register
banks in advance of running instruction selection.

Hope that helps
> On Jul 31, 2019, at 20:31, Nancy via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> 
> Hi,
> Can register class effect Instruction selection prefer in ISel pattern?
> 
> Example:
> Same LLVM IR add instruction, same data type i32, different asm
> instruction, different register class  GPR,  SGPR
> if one operator comes from GPR register class, it selects GPR
"add" instruction
> if all operators come from SGPR register class, it select SGPR
"add" instruction
> 
> 
> -- 
> Best Regards,
> Yu Rong Tan
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev