llvm dev - Jul 2019 - Having trouble getting started on writing a WDC 65816 backend

July 15, 2019 1:16 PM, "Bruce Hoult" <brucehoult at sifive.com>
wrote:
> Take, for example, RISC-V. You have 32 registers that, in the base
> fixed-length 32 bits long instruction set, are absolutely
> interchangeable with each other. No instructions use implicit source
> or destination registers, any register can be used for anything. There
> is no fixed stack pointer register -- any register can equally well be
> used as a stack pointer. There is no fixed function return link
> register -- any register can equally well be used as a link register.
> The only exception is that reads from register 0 always return 0 and
> writes to it are discarded. In general, if the compiler needs a
> register or some purpose it does not matter what the purpose is, the
> compiler can just grab the next available register and use it, without
> regard for what other registers are in use or what they are being used
> for.
> 
> Compare to 6502. There is a stack pointer that can't be directly
> accessed, but only used in push and pop and transferred to or from
> another register. There is a condition code register that can only be
> accessed implicitly or by pushing or popping it to the stack.
> Arithmetic such as add/siub/and/or/xor can only be done with the A
> register. Increment and decrement can only be done with the X and Y
> registers, not the A register. The (zp,reg) addressing mode can only
> be used with the X register. The (zp),reg addressing mode can only use
> the Y register.
Is it not the job of the backend to figure out how to use the registers
effectively? Or am I deeply misunderstanding how a backend is supposed to
transform IR?

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On Wed, Jul 17, 2019 at 12:42 PM Soren <me at s5.pm>
wrote:
>
> July 15, 2019 1:16 PM, "Bruce Hoult" <brucehoult at
sifive.com> wrote:
>
> > Take, for example, RISC-V. You have 32 registers that, in the base
> > fixed-length 32 bits long instruction set, are absolutely
> > interchangeable with each other. No instructions use implicit source
> > or destination registers, any register can be used for anything. There
> > is no fixed stack pointer register -- any register can equally well be
> > used as a stack pointer. There is no fixed function return link
> > register -- any register can equally well be used as a link register.
> > The only exception is that reads from register 0 always return 0 and
> > writes to it are discarded. In general, if the compiler needs a
> > register or some purpose it does not matter what the purpose is, the
> > compiler can just grab the next available register and use it, without
> > regard for what other registers are in use or what they are being used
> > for.
> >
> > Compare to 6502. There is a stack pointer that can't be directly
> > accessed, but only used in push and pop and transferred to or from
> > another register. There is a condition code register that can only be
> > accessed implicitly or by pushing or popping it to the stack.
> > Arithmetic such as add/siub/and/or/xor can only be done with the A
> > register. Increment and decrement can only be done with the X and Y
> > registers, not the A register. The (zp,reg) addressing mode can only
> > be used with the X register. The (zp),reg addressing mode can only use
> > the Y register.
>
> Is it not the job of the backend to figure out how to use the registers
> effectively? Or am I deeply misunderstanding how a backend is supposed to
> transform IR?
That is indeed the job of the backend, and it's an order of magnitude
harder when you have few registers and those registers have
specialized uses compared to when you have lots of registers and can
use any register for anything.