llvm dev - Jun 2019 - LLVM buildmaster will be off-line for about 30 minutes today at 5 pm

Hello everyone,

LLVM buildmaster will be off-line for about 30 minutes today after 5 pm PST
for maintenance.
Thank you for understanding.

Thanks



Galina
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Hello everyone,

I was investigating the buildbot e-mail notifications.

Some of you may receive old notifications, some might get some
notifications again.
Please ignore them. Sorry for the inconvenience and thanks for your
understanding.

Thanks

Galina



On Thu, Jun 20, 2019 at 3:41 PM Galina Kistanova <gkistanova at gmail.com>
wrote:
> Hello everyone,
>
> LLVM buildmaster will be off-line for about 30 minutes today after 5 pm
> PST for maintenance.
> Thank you for understanding.
>
> Thanks
>
>
>
> Galina
>
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Hi all LLVM expert,



I’m trying to ask how to bind hidden micro-architecture specific resource index
to architecture resource index in tablegen

There may be instruction uses 1 sr and 1 vr as source operand (using index
sr_src_idx, vr_src_idx), then uses 1 sr and 1 vr as destination (using index
sr_dst_idx, vr_dst_idx). Additionally, this instruction trigger a write to a
hidden resource whose index is same as the vr destination index (vr_dst_idx).
The instruction's write to SR/VR/HR are with different latency, say 1/3/6. 
Example code are as below

Is there a way to describe this in tablegen? How to bind the index between hr
and vr?

Scalar_Register sr[32]; //architecture visible resource

Vector_Register vr[32]; //architecture visible resource

Hidden_Resource hr[32]; //target specific micro-architecture resource, hidden
from architecture but impact performance

//instruction info defined in ISA

(VR vr_dst_idx, SR sr_dst_idx) = instruciton_1 (VR vr_src_idx, SR sr_src_idx) ;





Chuang Feng



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