Joan Lluch via llvm-dev
2019-May-28 19:35 UTC
[llvm-dev] Instruction is selected, but it shouldn't (?)
Hi Eli, Thanks for your response. Actually, I look a lot at the ARM and THUMB1 backend implementations, and this certainly help. My architecture also have specific instructions for SP-relative accesses in a similar way than the Thumb1. During frame lowering, specific machine instructions are emitted so there’s no issue there. Also during ISelDagToDag I am able to select the right instructions. The issue appears when trying to use the SP in iSelLowering, in particular, I attempt to create a LowerDYNAMIC_STACKALLOC function similar to the Thumb1. However, since my SP register is not part of the set of General Purpose registers, and the SP only has special instructions for it, I can NOT use the Thumb1 code implementation below: SDValue SP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32); Chain = SP.getValue(1); SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size); I must use this instead: SDValue SP = DAG.getRegister(CPU74::SP, VT); SP = DAG.getNode(ISD::SUB, dl, MVT::i16, SP, Size); The ‘getCopyFromReg’ code in the first excerpt produces suboptimal code because LLVM can not figure out a way to place the SP directly in the SUB instruction without using an intermediate register. However, the code on the second excerpt produces optimal code, except that the wrong instruction is selected… So, what do you suggest for me to do?. Maybe creating a Target Specific ISD instruction for that SUB that gets correctly selected during iSelDagToDag? Thanks. Joan Lluch> On 28 May 2019, at 20:55, Eli Friedman <efriedma at quicinc.com> wrote: > > SelectionDAG isel is only driven by types and operations; it doesn’t care about specific registers. So you have to pick one version of “add” you want isel to use by default (in this case, probably the general-register version), and only specify a pattern for that one. > > For computing the addresses of stack slots in particular, you might want to look at how the ARM backend generates Thumb1 code. Thumb1 has special instructions for SP-relative accesses (tADDframe, tADDrSP, tADDrSPi, tLDRspi, tSTRspi). Explicit copies from “sp” don’t really come up during isel, except for call arguments; most of the interesting code is part of frame lowering. > > -Eli > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Joan Lluch via llvm-dev > Sent: Tuesday, May 28, 2019 11:31 AM > To: via llvm-dev <llvm-dev at lists.llvm.org> > Subject: [EXT] [llvm-dev] Instruction is selected, but it shouldn't (?) > > In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register: > > def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>; > def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>; > > The SP can not be used in general purpose arithmetic instructions, therefore I defined the following classes in MyTargetInstrInfo.td: > > class T5rr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<4> opcode>: Type5 > <opcode, > (outs GR16:$rd), (ins GR16:$rn, GR16:$rs), > AsmStr< opcStr, altOpcStr, "\t$rn, $rs, $rd">.n, > [(set GR16:$rd, (opNode GR16:$rn, GR16:$rs)), (implicit SR)]>; > > I also have specific instructions that can only use the SP, so I defined this as well > > class T11sr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<3> opcode, bits<2> mode>: Type11 > <opcode, mode, > (outs GR16:$rd), (ins SSP:$sp, GR16:$rd0), > AsmStr< opcStr, altOpcStr, "\t$sp, $rd0, $rd">.n, > [(set GR16:$rd, (opNode SSP:$sp, GR16:$rd0)), (implicit SR)]> > {let Constraints = "$rd = $rd0";} > > > According to my understanding, instructions belonging to the T5rr16alu class above, should never be selected with the SP as register. However, instructions of that class get selected anyway with the SP, instead of the class T11sr16alu. > > However, if I place class T11sr16alu, before class T5rr16alu, then the right instruction is selected > > Why is that?. > What I am missing? > > Joan-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190528/81b8a853/attachment.html>
Eli Friedman via llvm-dev
2019-May-28 20:31 UTC
[llvm-dev] Instruction is selected, but it shouldn't (?)
You could create a target-specific instruction, or you could pattern-match the
copy+sub or copy+sub+copy combination in your Select() implementation in
ISelDAGToDAG. Or you could just ignore the potential optimization, like we do
on Thumb1; dynamic stack allocation is generally rare.
-Eli
From: Joan Lluch <joan.lluch at icloud.com>
Sent: Tuesday, May 28, 2019 12:36 PM
To: Eli Friedman <efriedma at quicinc.com>
Cc: llvm-dev <llvm-dev at lists.llvm.org>
Subject: [EXT] Re: [llvm-dev] Instruction is selected, but it shouldn't (?)
Hi Eli,
Thanks for your response. Actually, I look a lot at the ARM and THUMB1 backend
implementations, and this certainly help. My architecture also have specific
instructions for SP-relative accesses in a similar way than the Thumb1.
During frame lowering, specific machine instructions are emitted so there’s no
issue there. Also during ISelDagToDag I am able to select the right
instructions. The issue appears when trying to use the SP in iSelLowering, in
particular, I attempt to create a LowerDYNAMIC_STACKALLOC function similar to
the Thumb1. However, since my SP register is not part of the set of General
Purpose registers, and the SP only has special instructions for it, I can NOT
use the Thumb1 code implementation below:
SDValue SP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
Chain = SP.getValue(1);
SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size);
I must use this instead:
SDValue SP = DAG.getRegister(CPU74::SP, VT);
SP = DAG.getNode(ISD::SUB, dl, MVT::i16, SP, Size);
The ‘getCopyFromReg’ code in the first excerpt produces suboptimal code because
LLVM can not figure out a way to place the SP directly in the SUB instruction
without using an intermediate register.
However, the code on the second excerpt produces optimal code, except that the
wrong instruction is selected…
So, what do you suggest for me to do?. Maybe creating a Target Specific ISD
instruction for that SUB that gets correctly selected during iSelDagToDag?
Thanks.
Joan Lluch
On 28 May 2019, at 20:55, Eli Friedman <efriedma at
quicinc.com<mailto:efriedma at quicinc.com>> wrote:
SelectionDAG isel is only driven by types and operations; it doesn’t care about
specific registers. So you have to pick one version of “add” you want isel to
use by default (in this case, probably the general-register version), and only
specify a pattern for that one.
For computing the addresses of stack slots in particular, you might want to look
at how the ARM backend generates Thumb1 code. Thumb1 has special instructions
for SP-relative accesses (tADDframe, tADDrSP, tADDrSPi, tLDRspi, tSTRspi).
Explicit copies from “sp” don’t really come up during isel, except for call
arguments; most of the interesting code is part of frame lowering.
-Eli
From: llvm-dev <llvm-dev-bounces at lists.llvm.org<mailto:llvm-dev-bounces
at lists.llvm.org>> On Behalf Of Joan Lluch via llvm-dev
Sent: Tuesday, May 28, 2019 11:31 AM
To: via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at
lists.llvm.org>>
Subject: [EXT] [llvm-dev] Instruction is selected, but it shouldn't (?)
In MyTargetRegisterInfo.td file, I defined separated register classes for
general purpose registers and for the SP register:
def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3,
R4, R5, R6, R7)>;
def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>;
The SP can not be used in general purpose arithmetic instructions, therefore I
defined the following classes in MyTargetInstrInfo.td:
class T5rr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<4>
opcode>: Type5
<opcode,
(outs GR16:$rd), (ins GR16:$rn, GR16:$rs),
AsmStr< opcStr, altOpcStr, "\t$rn, $rs, $rd">.n,
[(set GR16:$rd, (opNode GR16:$rn, GR16:$rs)), (implicit
SR)]>;
I also have specific instructions that can only use the SP, so I defined this as
well
class T11sr16alu<string opcStr, string altOpcStr, SDNode opNode,
bits<3> opcode, bits<2> mode>: Type11
<opcode, mode,
(outs GR16:$rd), (ins SSP:$sp, GR16:$rd0),
AsmStr< opcStr, altOpcStr, "\t$sp, $rd0,
$rd">.n,
[(set GR16:$rd, (opNode SSP:$sp, GR16:$rd0)), (implicit SR)]>
{let Constraints = "$rd = $rd0";}
According to my understanding, instructions belonging to the T5rr16alu class
above, should never be selected with the SP as register. However, instructions
of that class get selected anyway with the SP, instead of the class T11sr16alu.
However, if I place class T11sr16alu, before class T5rr16alu, then the right
instruction is selected
Why is that?.
What I am missing?
Joan
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Joan Lluch via llvm-dev
2019-May-28 20:35 UTC
[llvm-dev] Instruction is selected, but it shouldn't (?)
Hi Eli, Ok, thank you very much. This is helpful. Joan Lluch Tel: 620 28 45 13> On 28 May 2019, at 22:31, Eli Friedman <efriedma at quicinc.com> wrote: > > You could create a target-specific instruction, or you could pattern-match the copy+sub or copy+sub+copy combination in your Select() implementation in ISelDAGToDAG. Or you could just ignore the potential optimization, like we do on Thumb1; dynamic stack allocation is generally rare. > -Eli > > From: Joan Lluch <joan.lluch at icloud.com <mailto:joan.lluch at icloud.com>> > Sent: Tuesday, May 28, 2019 12:36 PM > To: Eli Friedman <efriedma at quicinc.com <mailto:efriedma at quicinc.com>> > Cc: llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> > Subject: [EXT] Re: [llvm-dev] Instruction is selected, but it shouldn't (?) > > Hi Eli, > > Thanks for your response. Actually, I look a lot at the ARM and THUMB1 backend implementations, and this certainly help. My architecture also have specific instructions for SP-relative accesses in a similar way than the Thumb1. > > During frame lowering, specific machine instructions are emitted so there’s no issue there. Also during ISelDagToDag I am able to select the right instructions. The issue appears when trying to use the SP in iSelLowering, in particular, I attempt to create a LowerDYNAMIC_STACKALLOC function similar to the Thumb1. However, since my SP register is not part of the set of General Purpose registers, and the SP only has special instructions for it, I can NOT use the Thumb1 code implementation below: > > SDValue SP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32); > Chain = SP.getValue(1); > SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size); > > I must use this instead: > > SDValue SP = DAG.getRegister(CPU74::SP, VT); > SP = DAG.getNode(ISD::SUB, dl, MVT::i16, SP, Size); > > The ‘getCopyFromReg’ code in the first excerpt produces suboptimal code because LLVM can not figure out a way to place the SP directly in the SUB instruction without using an intermediate register. > > However, the code on the second excerpt produces optimal code, except that the wrong instruction is selected… > > So, what do you suggest for me to do?. Maybe creating a Target Specific ISD instruction for that SUB that gets correctly selected during iSelDagToDag? > > Thanks. > > Joan Lluch > > On 28 May 2019, at 20:55, Eli Friedman <efriedma at quicinc.com <mailto:efriedma at quicinc.com>> wrote: > > SelectionDAG isel is only driven by types and operations; it doesn’t care about specific registers. So you have to pick one version of “add” you want isel to use by default (in this case, probably the general-register version), and only specify a pattern for that one. > > For computing the addresses of stack slots in particular, you might want to look at how the ARM backend generates Thumb1 code. Thumb1 has special instructions for SP-relative accesses (tADDframe, tADDrSP, tADDrSPi, tLDRspi, tSTRspi). Explicit copies from “sp” don’t really come up during isel, except for call arguments; most of the interesting code is part of frame lowering. > > -Eli > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org <mailto:llvm-dev-bounces at lists.llvm.org>> On Behalf Of Joan Lluch via llvm-dev > Sent: Tuesday, May 28, 2019 11:31 AM > To: via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> > Subject: [EXT] [llvm-dev] Instruction is selected, but it shouldn't (?) > > In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register: > > def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>; > def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>; > > The SP can not be used in general purpose arithmetic instructions, therefore I defined the following classes in MyTargetInstrInfo.td: > > class T5rr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<4> opcode>: Type5 > <opcode, > (outs GR16:$rd), (ins GR16:$rn, GR16:$rs), > AsmStr< opcStr, altOpcStr, "\t$rn, $rs, $rd">.n, > [(set GR16:$rd, (opNode GR16:$rn, GR16:$rs)), (implicit SR)]>; > > I also have specific instructions that can only use the SP, so I defined this as well > > class T11sr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<3> opcode, bits<2> mode>: Type11 > <opcode, mode, > (outs GR16:$rd), (ins SSP:$sp, GR16:$rd0), > AsmStr< opcStr, altOpcStr, "\t$sp, $rd0, $rd">.n, > [(set GR16:$rd, (opNode SSP:$sp, GR16:$rd0)), (implicit SR)]> > {let Constraints = "$rd = $rd0";} > > > According to my understanding, instructions belonging to the T5rr16alu class above, should never be selected with the SP as register. However, instructions of that class get selected anyway with the SP, instead of the class T11sr16alu. > > However, if I place class T11sr16alu, before class T5rr16alu, then the right instruction is selected > > Why is that?. > What I am missing? > > Joan-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190528/dcfebf27/attachment-0001.html>