In the definition of register classes, have you provided any value types for each class? -Krzysztof On 1/9/2019 7:19 PM, m m via llvm-dev wrote:> The file that is causing this assertion contains only 3 include statements > > |//===-- ABCOther.td - Describe the ABC Target Machine ----*- tablegen > -*-===// // // > //===----------------------------------------------------------------------===// > // This is the top level entry point for the ABC target. > //===----------------------------------------------------------------------===// > //===----------------------------------------------------------------------===// > // Target-independent interfaces > //===----------------------------------------------------------------------===// > include "llvm/Target/Target.td" > //===----------------------------------------------------------------------===// > // Target-dependent interfaces > //===----------------------------------------------------------------------===// > include "ABCRegisterInfo.td" include "ABC.td" | > > > ------------------------------------------------------------------------ > *From:* Peter Teoh <htmldeveloper at gmail.com> > *Sent:* Sunday, January 6, 2019 12:10 AM > *To:* m m > *Cc:* via llvm-dev > *Subject:* Re: [llvm-dev] empty list assertion > sorry, ignore my earlier email. > > I followed this: > https://stackoverflow.com/questions/42881901/how-to-compile-some-modules-in-llvm-with-debug-mode-others-with-release-mode > and got the debug build completed. > > > > On Sat, Jan 5, 2019 at 10:02 AM Peter Teoh <htmldeveloper at gmail.com > <mailto:htmldeveloper at gmail.com>> wrote: > > will this help? > > https://opensource.apple.com/source/lldb/lldb-69/docs/building-with-debug-llvm.txt.auto.html > > On Sat, Jan 5, 2019 at 9:04 AM m m via llvm-dev > <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > Hi, > I'm trying to do a Debug build for the 1st time and I keep > getting this assertion: > > llvm-tblgen: CodeGenDAGPatterns.cpp:64: > llvm::EEVT::TypeSet::TypeSet(llvm::ArrayRef<llvm::MVT::SimpleValueType>): > Assertion `!VTList.empty() && "empty list?"' failed. > > I do not know what list this assertion is referring to. Does > anyone know? I always did Release builds before without any > problem. > > Thanks. > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > > > > -- > Regards, > Peter Teoh > > > > -- > Regards, > Peter Teoh > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Krzysztof,
Sorry I'm new to LLVM and not sure what a 'value type' is.
I have 2 register classes and they are defined like this:
def CPURegs : RegisterClass<"ABC", [i32], 32, (add R0, R1, R3,
R4)>;
def CFRegs : RegisterClass<"ABC", [i1], 8, (add CF)>
{
let isAllocatable = 0;
let Size = 8;
}
Thanks
________________________________
From: llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of Krzysztof
Parzyszek via llvm-dev <llvm-dev at lists.llvm.org>
Sent: Thursday, January 10, 2019 11:28 AM
To: llvm-dev at lists.llvm.org
Subject: Re: [llvm-dev] empty list assertion
In the definition of register classes, have you provided any value types
for each class?
-Krzysztof
On 1/9/2019 7:19 PM, m m via llvm-dev wrote:> The file that is causing this assertion contains only 3 include statements
>
> |//===-- ABCOther.td - Describe the ABC Target Machine ----*- tablegen
> -*-===// // //
>
//===----------------------------------------------------------------------===//
> // This is the top level entry point for the ABC target.
>
//===----------------------------------------------------------------------===//
>
//===----------------------------------------------------------------------===//
> // Target-independent interfaces
>
//===----------------------------------------------------------------------===//
> include "llvm/Target/Target.td"
>
//===----------------------------------------------------------------------===//
> // Target-dependent interfaces
>
//===----------------------------------------------------------------------===//
> include "ABCRegisterInfo.td" include "ABC.td" |
>
>
> ------------------------------------------------------------------------
> *From:* Peter Teoh <htmldeveloper at gmail.com>
> *Sent:* Sunday, January 6, 2019 12:10 AM
> *To:* m m
> *Cc:* via llvm-dev
> *Subject:* Re: [llvm-dev] empty list assertion
> sorry, ignore my earlier email.
>
> I followed this:
>
https://stackoverflow.com/questions/42881901/how-to-compile-some-modules-in-llvm-with-debug-mode-others-with-release-mode
> and got the debug build completed.
>
>
>
> On Sat, Jan 5, 2019 at 10:02 AM Peter Teoh <htmldeveloper at gmail.com
> <mailto:htmldeveloper at gmail.com>> wrote:
>
> will this help?
>
>
https://opensource.apple.com/source/lldb/lldb-69/docs/building-with-debug-llvm.txt.auto.html
>
> On Sat, Jan 5, 2019 at 9:04 AM m m via llvm-dev
> <llvm-dev at lists.llvm.org <mailto:llvm-dev at
lists.llvm.org>> wrote:
>
> Hi,
> I'm trying to do a Debug build for the 1st time and I keep
> getting this assertion:
>
> llvm-tblgen: CodeGenDAGPatterns.cpp:64:
>
llvm::EEVT::TypeSet::TypeSet(llvm::ArrayRef<llvm::MVT::SimpleValueType>):
> Assertion `!VTList.empty() && "empty list?"'
failed.
>
> I do not know what list this assertion is referring to. Does
> anyone know? I always did Release builds before without any
> problem.
>
> Thanks.
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org <mailto:llvm-dev at
lists.llvm.org>
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>
>
> --
> Regards,
> Peter Teoh
>
>
>
> --
> Regards,
> Peter Teoh
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
_______________________________________________
LLVM Developers mailing list
llvm-dev at lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
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On 1/10/2019 10:38 PM, m m wrote:> > Sorry I'm new to LLVM and not sure what a 'value type' is. > I have 2 register classes and they are defined like this: > > def CPURegs : RegisterClass<"ABC", [i32], 32, (add R0, R1, R3, R4)>; > > def CFRegs : RegisterClass<"ABC", [i1], 8, (add CF)> > { > let isAllocatable = 0; > let Size = 8; > } >By "value type" I meant "MachineValueType", which is a low-level representation of a type. It's easier to understand what it is by simply looking in MachineValueType.h: these are things like i8 or i32 (representing 8- and 32-bit integers), or f32 (for 32-bit floating point), etc. Each definition of a register class will have a set of value types that registers from that class can hold. This set will be used in the instruction selection to pick an appropriate register to hold a value of a given type. It seems like in your case the value type lists are there, so the assertion is likely coming from somewhere else. On that note, you seem to be using a very old version of LLVM. Do you have a reason for that? If not, try updating the LLVM sources---many things have changed since then, including parts of LLVM that are related to the problem you're seeing. I don't know if the problem would go away, but it would be easier for you to get help with it, if it's still present. -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation