llvm dev - Apr 2018 - liveness tracking of a register class with a single sub-register

Hi list.

I'm trying to enable sub-register liveness tracking for our target but
I'm hitting the following assert on VirtRegRewriter::readsUndefSubreg:

  assert(SubRegIdx != 0 && LI.hasSubRanges());

The reason is that I have a register class of two bit predicates where only the
low bit is allocatable so there's only a single sub-register.
Now, MachineRegisterInfo only enables sub-reg liveness tracking for a class if
it has at least two distinct sub-registers,
so the live range cannot have sub-ranges in this case but instructions can read
the single sub-reg nevertheless, which leads to this assertion failing.

Has anyone ran into this problem before or know of an in-tree target which has a
similar construct?

Thanks,
Dvir
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