llvm dev - Mar 2016 - generate vectorized code

> On Mar 18, 2016, at 12:52 PM, Mehdi Amini <mehdi.amini at apple.com>
wrote:
> 
>> 
>> On Mar 18, 2016, at 12:45 PM, Rail Shafigulin <rail at
esenciatech.com <mailto:rail at esenciatech.com>> wrote:
>> 
>> On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at
esenciatech.com <mailto:rail at esenciatech.com>> wrote:
>> On Thu, Mar 17, 2016 at 10:10 AM, Rail Shafigulin <rail at
esenciatech.com <mailto:rail at esenciatech.com>> wrote:
>> On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at
apple.com <mailto:mehdi.amini at apple.com>> wrote:
>> 
>>> On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at
esenciatech.com <mailto:rail at esenciatech.com>> wrote:
>>> 
>>> On Wed, Mar 16, 2016 at 11:48 AM, Mehdi Amini <mehdi.amini at
apple.com <mailto:mehdi.amini at apple.com>> wrote:
>>> Hi Rail,
>>> 
>>> Two hints to begin with:
>>> 
>>> 1) Makes sure you example is vectorized on X86 for example
>>> 2) Is your target correctly overriding the TTI (declaring the
vector register size for example) so that the vectorizer can kicks-in (see
X86TTIImpl::getRegisterBitWidth for instance). Alternatively you can test the
SLP vectorizer by passing to clang: -mllvm -slp-max-reg-size -mllvm 512  (I
don't see an equivalent option for the loop vectorizer though).
>>> 
>>> Well, it sort of worked. I added a getRegisterBitWidth(...) but
then I got this error:
>>> 
>>> fatal error: error in backend: Cannot select: 0x5e949a8: v4i32 =
BUILD_VECTOR 0x5e91ae8, 0x5e91ae8, 0x5e91ae8, 0x5e91ae8 [ORD=16] [ID=16]
>>>   0x5e91ae8: i32 = Constant<0> [ID=5]
>>>   0x5e91ae8: i32 = Constant<0> [ID=5]
>>>   0x5e91ae8: i32 = Constant<0> [ID=5]
>>>   0x5e91ae8: i32 = Constant<0> [ID=5]
>>> 
>>> What am I missing?
>> 
>> I means that you have a vectorized IR that reached your backend, but
your backend is not ready to deal with all the vector constructs in
SelectionDAG.
>> You need to express how to legalize/select the BUILD_VECTOR in
SelectionDAG to instructions that your target supports. You can look at what
other targets are doing.
>> 
>> -- 
>> Mehdi
>> 
>> 
>> So I've added setOperationAction(ISD::BUILD_VECTOR,     
MVT::v4i32, Expand); to my code but that generated a following error:
>> 
>> fatal error: error in backend: Cannot select: 0x6a84dc8: i32 =
extract_vector_elt 0x6a85388, 0x6a813b0 [ORD=9] [ID=16]
>>   0x6a85388: v4i32 = add 0x6a81098, 0x6a81e00 [ORD=8] [ID=15]
>>     0x6a81098: v4i32 = add 0x6a81bf0, 0x6a84168 [ORD=6] [ID=12]
>>       0x6a81bf0: v4i32,ch = CopyFromReg 0x6a2b7f0, 0x6a819e0 [ORD=5]
[ID=8]
>>         0x6a819e0: v4i32 = Register %vreg4 [ID=1]
>>       0x6a84168: v4i32 = vector_shuffle 0x6a81bf0,
0x6a857a8<2,3,u,u> [ORD=5] [ID=10]
>>         0x6a81bf0: v4i32,ch = CopyFromReg 0x6a2b7f0, 0x6a819e0 [ORD=5]
[ID=8]
>>           0x6a819e0: v4i32 = Register %vreg4 [ID=1]
>>         0x6a857a8: v4i32 = undef [ID=2]
>>     0x6a81e00: v4i32 = vector_shuffle 0x6a81098,
0x6a857a8<1,u,u,u> [ORD=7] [ID=14]
>>       0x6a81098: v4i32 = add 0x6a81bf0, 0x6a84168 [ORD=6] [ID=12]
>>         0x6a81bf0: v4i32,ch = CopyFromReg 0x6a2b7f0, 0x6a819e0 [ORD=5]
[ID=8]
>>           0x6a819e0: v4i32 = Register %vreg4 [ID=1]
>>         0x6a84168: v4i32 = vector_shuffle 0x6a81bf0,
0x6a857a8<2,3,u,u> [ORD=5] [ID=10]
>>           0x6a81bf0: v4i32,ch = CopyFromReg 0x6a2b7f0, 0x6a819e0
[ORD=5] [ID=8]
>>             0x6a819e0: v4i32 = Register %vreg4 [ID=1]
>>           0x6a857a8: v4i32 = undef [ID=2]
>>       0x6a857a8: v4i32 = undef [ID=2]
>>   0x6a813b0: i32 = Constant<0> [ID=3]
>> In function: main
>> 
>> Then I've added
>> setOperationAction(ISD::EXTRACT_VECTOR_ELT,      MVT::i32, Expand);
>> 
>> but I still got the same error. So removed
setOperationAction(ISD::EXTRACT_VECTOR_ELT,      MVT::i32, Expand); and added
>> 
>> setOperationAction(ISD::EXTRACT_VECTOR_ELT,      MVT::v4i32, Expand);
>> 
>> which produced a following error:
>> 
>> fatal error: error in backend: Cannot select: 0x7389250: v4i32 =
vector_shuffle 0x73884e8, 0x738cbf8<1,u,u,u> [ORD=7] [ID=15]
>>   0x73884e8: v4i32 = add 0x7389040, 0x738b5b8 [ORD=6] [ID=13]
>>     0x7389040: v4i32,ch = CopyFromReg 0x73327f0, 0x7388e30 [ORD=5]
[ID=9]
>>       0x7388e30: v4i32 = Register %vreg4 [ID=1]
>>     0x738b5b8: v4i32 = vector_shuffle 0x7389040,
0x738cbf8<2,3,u,u> [ORD=5] [ID=11]
>>       0x7389040: v4i32,ch = CopyFromReg 0x73327f0, 0x7388e30 [ORD=5]
[ID=9]
>>         0x7388e30: v4i32 = Register %vreg4 [ID=1]
>>       0x738cbf8: v4i32 = undef [ID=2]
>>   0x738cbf8: v4i32 = undef [ID=2]
>> In function: main
>> 
>> Then I'v added setOperationAction(ISD::VECTOR_SHUFFLE,     
MVT::v4i32, Expand);
>> 
>> and then my clang just hang. There is no error, no warning clang just
sits there and nothing happens.
> 
> 
> I think you created a cycle, this is easy to do with SelectionDAG :)
> Basically SelecitonDAG will iterate until it does not see anything to
change. So if you insert a transformation on a pattern A, that generates pattern
B, while you have another transformation that matches B and generates somehow A,
you run into an infinite loop.
> 
> 
> 
>> 
>> I'm doing a lot of guess work in trying to understand what is going
on. I would really appreciate any help on this.
> 
> Here is how I started with SelectionDAG: 
> 
> - small IR (bugpoint can help)
> - the magic flag: -debug 
> - read the output of SelectionDAG debugging (especially with cycles)
> - matching the log to source code
> - single stepping in a debugger sometimes.
Also: try to run your experiments with llc so you can easily tweak the input IR
to SelectionDAG.

-- 
Mehdi

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>
> I think you created a cycle, this is easy to do with SelectionDAG :)
> Basically SelecitonDAG will iterate until it does not see anything to
> change. So if you insert a transformation on a pattern A, that generates
> pattern B, while you have another transformation that matches B and
> generates somehow A, you run into an infinite loop.
>
>
>
>
> I'm doing a lot of guess work in trying to understand what is going on.
I
> would really appreciate any help on this.
>
>
> Here is how I started with SelectionDAG:
>
> - small IR (bugpoint can help)
> - the magic flag: -debug
> - read the output of SelectionDAG debugging (especially with cycles)
> - matching the log to source code
> - single stepping in a debugger sometimes.
>
>
> Also: try to run your experiments with llc so you can easily tweak the
> input IR to SelectionDAG.
>
> --
> Mehdi
>
>
I ran a very simple test using llc and the following .ll file
target datalayout =
"E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32"
target triple = "esencia"

; Function Attrs: nounwind uwtable
define i32 @main() {
entry:
   %z = alloca <4 x i32>
   %a = alloca <4 x i32>
   %b = alloca <4 x i32>
   %a.l = load <4 x i32>* %a
   %b.l = load <4 x i32>* %b
   %z.l = add <4 x i32> %a.l, %b.l
   store <4 x i32> %z.l, <4 x i32>* %z
   ret i32 0
}

The test ran successfully (by successfully I mean genration of correct
assembly for my target) without any modifications to the code, i.e. I
didn't have to add any
  setOperationAction(ISD::BUILD_VECTOR,      MVT::v4i32, Expand);
  setOperationAction(ISD::EXTRACT_VECTOR_ELT,      MVT::v4i32, Expand);
  setOperationAction(ISD::VECTOR_SHUFFLE,      MVT::v4i32, Expand);

In other words I left the code as is.

However if I use a .c code and run it through clang, I don't see any vector
instructions. I'm puzzled. What am I doing wrong? There seems to be a step
missing, the one that will generate vectorized IR, but I can't seem to find
how to do it.

Any help on this is really appreciated.

-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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> On Mar 18, 2016, at 1:37 PM, Rail Shafigulin <rail at
esenciatech.com> wrote:
> 
>> I think you created a cycle, this is easy to do with SelectionDAG :)
>> Basically SelecitonDAG will iterate until it does not see anything to
change. So if you insert a transformation on a pattern A, that generates pattern
B, while you have another transformation that matches B and generates somehow A,
you run into an infinite loop.
>> 
>> 
>> 
>>> 
>>> I'm doing a lot of guess work in trying to understand what is
going on. I would really appreciate any help on this.
>> 
>> Here is how I started with SelectionDAG: 
>> 
>> - small IR (bugpoint can help)
>> - the magic flag: -debug 
>> - read the output of SelectionDAG debugging (especially with cycles)
>> - matching the log to source code
>> - single stepping in a debugger sometimes.
> 
> Also: try to run your experiments with llc so you can easily tweak the
input IR to SelectionDAG.
> 
> -- 
> Mehdi
> 
> 
> 
> I ran a very simple test using llc and the following .ll file
> target datalayout =
"E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32"
> target triple = "esencia"
> 
> ; Function Attrs: nounwind uwtable
> define i32 @main() {
> entry:
>    %z = alloca <4 x i32>
>    %a = alloca <4 x i32>
>    %b = alloca <4 x i32>
>    %a.l = load <4 x i32>* %a
>    %b.l = load <4 x i32>* %b
>    %z.l = add <4 x i32> %a.l, %b.l
>    store <4 x i32> %z.l, <4 x i32>* %z
>    ret i32 0
> }
> 
> The test ran successfully (by successfully I mean genration of correct
assembly for my target) without any modifications to the code, i.e. I didn't
have to add any
>   setOperationAction(ISD::BUILD_VECTOR,      MVT::v4i32, Expand);
>   setOperationAction(ISD::EXTRACT_VECTOR_ELT,      MVT::v4i32, Expand);
>   setOperationAction(ISD::VECTOR_SHUFFLE,      MVT::v4i32, Expand);

Yes this IR does not build or shuffle any vector. Try to write a function that
takes 8 ints and a pointer to a <4xi32>, builds two vectors with the 8
ints, sum them, and store the result to the pointer.

> 
> In other words I left the code as is. 
> 
> However if I use a .c code and run it through clang, I don't see any
vector instructions. I'm puzzled. What am I doing wrong? There seems to be a
step missing, the one that will generate vectorized IR, but I can't seem to
find how to do it.
Try: clang -O3 -emit-llvm -S test.c

-- 
Mehdi

> 
> Any help on this is really appreciated.
> 
> -- 
> Rail Shafigulin
> Software Engineer 
> Esencia Technologies
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