llvm dev - Mar 2016 - Instructions with register constraints

I'm porting a new LLVM target.
My ISA has an 'add333 $rd3, $rt3, $rs3 ' instruction which acts as
'add $rd5, $rt5, $rs5'.
$rd5, $rt5, and $rs5 are register operands with 5-bit encoding space,
thus  they can access register from $r0 to $r31 belong to GPR register
class.
However, $rd3, $rt3, and $rs3 are register operands with only 3-bit
encoding space; in other word, they can only access registers from $r0
to $r7 belong to the same GPR register class.
I have no idea how to describe this kind of register constraints.

Please kindly guide me the direction.
Thanks in advance.

On 3/14/2016 1:51 AM, Pei-Shiang Hung via llvm-dev
wrote:
> I'm porting a new LLVM target.
> My ISA has an 'add333 $rd3, $rt3, $rs3 ' instruction which acts as
> 'add $rd5, $rt5, $rs5'.
> $rd5, $rt5, and $rs5 are register operands with 5-bit encoding space,
> thus  they can access register from $r0 to $r31 belong to GPR register
> class.
> However, $rd3, $rt3, and $rs3 are register operands with only 3-bit
> encoding space; in other word, they can only access registers from $r0
> to $r7 belong to the same GPR register class.
> I have no idea how to describe this kind of register constraints.
You can define a "3-bit" subclass of the "5-bit" register
class.  For
example, if the registers $r0..$r31 belong to a register class GPR5, you 
can define a register class GPR3 that is contained in GPR5, that only 
has $r0..$r7 as members.

-Krzysztof


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