Rail Shafigulin via llvm-dev
2016-Feb-17 20:25 UTC
[llvm-dev] Hexagon, inline assembly and packetization
I'm not very clear on how exactly does Hexagon handle inline assembly during packetization pass and afterwards. Say there are several instructions in inline assembly. Will Hexagon split them and packetize using dependencies? Will it create a packet for every instruction in the inline assembly? Would anyone be able to provide any insights. Help is greatly appreciated. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160217/c867f35d/attachment.html>
Colin LeMahieu via llvm-dev
2016-Feb-17 20:52 UTC
[llvm-dev] Hexagon, inline assembly and packetization
Packets when specified in assembly are delineated by curly braces. If the braces are omitted there is one instruction per packet. One packet two instructions: { r0 = add(r0, r0) r1 = add(r1, r1) } Two packets, one instruction each. r0 = add(r0, r0) r1 = add(r1, r1) From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Rail Shafigulin via llvm-dev Sent: Wednesday, February 17, 2016 2:26 PM To: llvm-dev Subject: [llvm-dev] Hexagon, inline assembly and packetization I'm not very clear on how exactly does Hexagon handle inline assembly during packetization pass and afterwards. Say there are several instructions in inline assembly. Will Hexagon split them and packetize using dependencies? Will it create a packet for every instruction in the inline assembly? Would anyone be able to provide any insights. Help is greatly appreciated. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160217/6ec46925/attachment.html>
Krzysztof Parzyszek via llvm-dev
2016-Feb-17 21:35 UTC
[llvm-dev] Hexagon, inline assembly and packetization
On 2/17/2016 2:25 PM, Rail Shafigulin via llvm-dev wrote:> I'm not very clear on how exactly does Hexagon handle inline assembly > during packetization pass and afterwards. Say there are several > instructions in inline assembly. Will Hexagon split them and packetize > using dependencies? Will it create a packet for every instruction in the > inline assembly? Would anyone be able to provide any insights.Inline assembly is treated as a "solo" instruction in the packetizer. -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation