llvm dev - Feb 2016 - Assigning constant value without alloca/load/store

Hello,

I am currently trying to translate some custom IR to LLVM-IR and came
across and issue.
The custom IR has several registers and I am basically try to SSAfy it so
it can be easily translated/converted to LLVM-IR.

The problem:

Since in my custom IR I can reassign every register I have to reassign
every new expression with a new llvm Value. But my IR has something like
this:

REG A = VAR C + CONST 2
REG A = CONST 12

So my workaround looks like:

; I am returning the registers in an anonymous struct
define { i32, i32, i32 } @test(i32 %var_c) {
  ; Initializing registers
  %reg_a_0 = select i1 true, i32 0, i32 0
  %reg_b_0 = select i1 true, i32 0, i32 0
  %reg_c_0 = select i1 true, i32 0, i32 0

  ; Translated instructions
  %reg_a_1 = add i32 %var_c, 2
  %reg_a_2 = select i1 true, i32 12, i32 0

  ; Prepare return values
  %ret_0 = insertvalue { i32, i32, i32 } undef, i32 %reg_a_2, 0
  %ret_1 = insertvalue { i32, i32, i32 } %ret_0, i32 %reg_b_0, 1
  %ret_2 = insertvalue { i32, i32, i32 } %ret_1, i32 %reg_c_0, 2

  ret { i32, i32, i32 } %ret_2
}

I am basically using "select i1 true, i32 1, i32 0" so after
optimization
it gets:
%val = i32 1

But as I said this looks like a hack to me and I can't simply use "%val
i32 1".
So what's the proper way to do this without actually using
alloca/load/store.

Regards,
Paul
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Hi!

I don't know what "the right way" to do this is, but is there any
reason
you're against just using alloca/load/store? That's what clang emits for
most locals/parameters/..., and LLVM tends to do a very good job of
SSAifying that where it can. :)

George

On Sun, Feb 7, 2016 at 3:00 PM, Paul Peet via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hello,
>
> I am currently trying to translate some custom IR to LLVM-IR and came
> across and issue.
> The custom IR has several registers and I am basically try to SSAfy it so
> it can be easily translated/converted to LLVM-IR.
>
> The problem:
>
> Since in my custom IR I can reassign every register I have to reassign
> every new expression with a new llvm Value. But my IR has something like
> this:
>
> REG A = VAR C + CONST 2
> REG A = CONST 12
>
> So my workaround looks like:
>
> ; I am returning the registers in an anonymous struct
> define { i32, i32, i32 } @test(i32 %var_c) {
>   ; Initializing registers
>   %reg_a_0 = select i1 true, i32 0, i32 0
>   %reg_b_0 = select i1 true, i32 0, i32 0
>   %reg_c_0 = select i1 true, i32 0, i32 0
>
>   ; Translated instructions
>   %reg_a_1 = add i32 %var_c, 2
>   %reg_a_2 = select i1 true, i32 12, i32 0
>
>   ; Prepare return values
>   %ret_0 = insertvalue { i32, i32, i32 } undef, i32 %reg_a_2, 0
>   %ret_1 = insertvalue { i32, i32, i32 } %ret_0, i32 %reg_b_0, 1
>   %ret_2 = insertvalue { i32, i32, i32 } %ret_1, i32 %reg_c_0, 2
>
>   ret { i32, i32, i32 } %ret_2
> }
>
> I am basically using "select i1 true, i32 1, i32 0" so after
optimization
> it gets:
> %val = i32 1
>
> But as I said this looks like a hack to me and I can't simply use
"%val > i32 1".
> So what's the proper way to do this without actually using
> alloca/load/store.
>
> Regards,
> Paul
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>
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On Sun, Feb 7, 2016 at 3:00 PM, Paul Peet via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hello,
>
> I am currently trying to translate some custom IR to LLVM-IR and came
> across and issue.
> The custom IR has several registers and I am basically try to SSAfy it so
> it can be easily translated/converted to LLVM-IR.
>
> The problem:
>
> Since in my custom IR I can reassign every register I have to reassign
> every new expression with a new llvm Value. But my IR has something like
> this:
>
> REG A = VAR C + CONST 2
> REG A = CONST 12
>
> So my workaround looks like:
>
> ; I am returning the registers in an anonymous struct
> define { i32, i32, i32 } @test(i32 %var_c) {
>   ; Initializing registers
>   %reg_a_0 = select i1 true, i32 0, i32 0
>   %reg_b_0 = select i1 true, i32 0, i32 0
>   %reg_c_0 = select i1 true, i32 0, i32 0
>
>   ; Translated instructions
>   %reg_a_1 = add i32 %var_c, 2
>   %reg_a_2 = select i1 true, i32 12, i32 0
>
>   ; Prepare return values
>   %ret_0 = insertvalue { i32, i32, i32 } undef, i32 %reg_a_2, 0
>   %ret_1 = insertvalue { i32, i32, i32 } %ret_0, i32 %reg_b_0, 1
>   %ret_2 = insertvalue { i32, i32, i32 } %ret_1, i32 %reg_c_0, 2
>
>   ret { i32, i32, i32 } %ret_2
> }
>
> I am basically using "select i1 true, i32 1, i32 0" so after
optimization
> it gets:
> %val = i32 1
>
> But as I said this looks like a hack to me and I can't simply use
"%val > i32 1".
> So what's the proper way to do this without actually using
> alloca/load/store.
>
You can use trivial bitcasts if you want to avoid load/store/alloca and you
want SSA variables for your constants:
  %val = bitcast i32 1 to i32

>
> Regards,
> Paul
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>
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IMHO, don't try to tell llvm about your registers, instead create a mapping
between the last Value* assigned to each register for each basic block.

For example, here's a crude suggestion.

First pass, identify all of the branch destinations from your custom IR,
where you will need to create an llvm basic block.

Second pass, translate IR instructions into llvm IR for each block.
 - keep track of the last Value* stored in each register.
 - if you need to load a Value* from a register that hasn't been assigned
yet in this block, create a phi node and insert it at the start of the
block.

Third pass, follow branches and link up phi nodes.


Or you could simply generate code as if each register is on the stack.
Generating alloca, load & store. Then run the mem2reg pass to promote
everything back to virtual registers for you automatically. That's probably
easier to get right.






On Mon, Feb 8, 2016 at 9:30 AM, Paul Peet via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hello,
>
> I am currently trying to translate some custom IR to LLVM-IR and came
> across and issue.
> The custom IR has several registers and I am basically try to SSAfy it so
> it can be easily translated/converted to LLVM-IR.
>
> The problem:
>
> Since in my custom IR I can reassign every register I have to reassign
> every new expression with a new llvm Value. But my IR has something like
> this:
>
> REG A = VAR C + CONST 2
> REG A = CONST 12
>
> So my workaround looks like:
>
> ; I am returning the registers in an anonymous struct
> define { i32, i32, i32 } @test(i32 %var_c) {
>   ; Initializing registers
>   %reg_a_0 = select i1 true, i32 0, i32 0
>   %reg_b_0 = select i1 true, i32 0, i32 0
>   %reg_c_0 = select i1 true, i32 0, i32 0
>
>   ; Translated instructions
>   %reg_a_1 = add i32 %var_c, 2
>   %reg_a_2 = select i1 true, i32 12, i32 0
>
>   ; Prepare return values
>   %ret_0 = insertvalue { i32, i32, i32 } undef, i32 %reg_a_2, 0
>   %ret_1 = insertvalue { i32, i32, i32 } %ret_0, i32 %reg_b_0, 1
>   %ret_2 = insertvalue { i32, i32, i32 } %ret_1, i32 %reg_c_0, 2
>
>   ret { i32, i32, i32 } %ret_2
> }
>
> I am basically using "select i1 true, i32 1, i32 0" so after
optimization
> it gets:
> %val = i32 1
>
> But as I said this looks like a hack to me and I can't simply use
"%val > i32 1".
> So what's the proper way to do this without actually using
> alloca/load/store.
>
> Regards,
> Paul
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>
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This looks much better than using "select i1 true, i32 1, i32 0".
But since something like that (bitcast constant) is allowed why isn't it
possible to simply do this:
%val = i32 1
?

2016-02-08 7:45 GMT+01:00 David Majnemer <david.majnemer at gmail.com>:
>
>
> On Sun, Feb 7, 2016 at 3:00 PM, Paul Peet via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hello,
>>
>> I am currently trying to translate some custom IR to LLVM-IR and came
>> across and issue.
>> The custom IR has several registers and I am basically try to SSAfy it
so
>> it can be easily translated/converted to LLVM-IR.
>>
>> The problem:
>>
>> Since in my custom IR I can reassign every register I have to reassign
>> every new expression with a new llvm Value. But my IR has something
like
>> this:
>>
>> REG A = VAR C + CONST 2
>> REG A = CONST 12
>>
>> So my workaround looks like:
>>
>> ; I am returning the registers in an anonymous struct
>> define { i32, i32, i32 } @test(i32 %var_c) {
>>   ; Initializing registers
>>   %reg_a_0 = select i1 true, i32 0, i32 0
>>   %reg_b_0 = select i1 true, i32 0, i32 0
>>   %reg_c_0 = select i1 true, i32 0, i32 0
>>
>>   ; Translated instructions
>>   %reg_a_1 = add i32 %var_c, 2
>>   %reg_a_2 = select i1 true, i32 12, i32 0
>>
>>   ; Prepare return values
>>   %ret_0 = insertvalue { i32, i32, i32 } undef, i32 %reg_a_2, 0
>>   %ret_1 = insertvalue { i32, i32, i32 } %ret_0, i32 %reg_b_0, 1
>>   %ret_2 = insertvalue { i32, i32, i32 } %ret_1, i32 %reg_c_0, 2
>>
>>   ret { i32, i32, i32 } %ret_2
>> }
>>
>> I am basically using "select i1 true, i32 1, i32 0" so after
optimization
>> it gets:
>> %val = i32 1
>>
>> But as I said this looks like a hack to me and I can't simply use
"%val >> i32 1".
>> So what's the proper way to do this without actually using
>> alloca/load/store.
>>
>
> You can use trivial bitcasts if you want to avoid load/store/alloca and
> you want SSA variables for your constants:
>   %val = bitcast i32 1 to i32
>
>
>>
>> Regards,
>> Paul
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
>>
>
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I want to keep the translation short and simple (My IR doesn't have control
flow so it's basically on basic block) that's why I don't want to
rely on
alloca/load/store.

2016-02-08 6:08 GMT+01:00 George Burgess IV <george.burgess.iv at
gmail.com>:
> Hi!
>
> I don't know what "the right way" to do this is, but is there
any reason
> you're against just using alloca/load/store? That's what clang
emits for
> most locals/parameters/..., and LLVM tends to do a very good job of
> SSAifying that where it can. :)
>
> George
>
> On Sun, Feb 7, 2016 at 3:00 PM, Paul Peet via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hello,
>>
>> I am currently trying to translate some custom IR to LLVM-IR and came
>> across and issue.
>> The custom IR has several registers and I am basically try to SSAfy it
so
>> it can be easily translated/converted to LLVM-IR.
>>
>> The problem:
>>
>> Since in my custom IR I can reassign every register I have to reassign
>> every new expression with a new llvm Value. But my IR has something
like
>> this:
>>
>> REG A = VAR C + CONST 2
>> REG A = CONST 12
>>
>> So my workaround looks like:
>>
>> ; I am returning the registers in an anonymous struct
>> define { i32, i32, i32 } @test(i32 %var_c) {
>>   ; Initializing registers
>>   %reg_a_0 = select i1 true, i32 0, i32 0
>>   %reg_b_0 = select i1 true, i32 0, i32 0
>>   %reg_c_0 = select i1 true, i32 0, i32 0
>>
>>   ; Translated instructions
>>   %reg_a_1 = add i32 %var_c, 2
>>   %reg_a_2 = select i1 true, i32 12, i32 0
>>
>>   ; Prepare return values
>>   %ret_0 = insertvalue { i32, i32, i32 } undef, i32 %reg_a_2, 0
>>   %ret_1 = insertvalue { i32, i32, i32 } %ret_0, i32 %reg_b_0, 1
>>   %ret_2 = insertvalue { i32, i32, i32 } %ret_1, i32 %reg_c_0, 2
>>
>>   ret { i32, i32, i32 } %ret_2
>> }
>>
>> I am basically using "select i1 true, i32 1, i32 0" so after
optimization
>> it gets:
>> %val = i32 1
>>
>> But as I said this looks like a hack to me and I can't simply use
"%val >> i32 1".
>> So what's the proper way to do this without actually using
>> alloca/load/store.
>>
>> Regards,
>> Paul
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
>>
>
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