Thanks, Igor and Elena!
On Mon, Jan 25, 2016 at 4:28 AM, Breger, Igor <igor.breger at intel.com>
wrote:
> Hello,
>
> Enabling vector masked_load/store to AVX1 using AVX1 FP instructions
> (vmaskmovps/pd) in place of the AVX2 int instructions (vpmaskmovd/q)
>
> committed to r258675. (http://reviews.llvm.org/D16528)
>
>
>
> Regards,
>
> Igor Breger.
>
>
>
>
>
>
>
> *From:* Sanjay Patel [mailto:spatel at rotateright.com
> <spatel at rotateright.com>]
> *Sent:* Saturday, January 23, 2016 18:42
> *To:* Nema, Ashutosh <Ashutosh.Nema at amd.com>
> *Cc:* Demikhovsky, Elena <elena.demikhovsky at intel.com>; zhi chen
<
> zchenhn at gmail.com>; llvm-dev <llvm-dev at lists.llvm.org>
> *Subject:* Re: [llvm-dev] how to force llvm generate gather intrinsic
>
>
>
>
>
> On Sat, Jan 23, 2016 at 6:45 AM, Nema, Ashutosh <Ashutosh.Nema at
amd.com>
> wrote:
>
> Thanks Sanjay for highlighting this, few days back I also faced similar
> problem
>
> while generating masked store in avx1 mode, found its only supported under
>
> avx2 else we scalarize it.
>
>
>
> > 1) I did not switch-on masked_load/store to AVX1, I can do this.
>
>
>
> Yes Elena, This should be supported for FP type in avx1 mode (for INT
> type, I doubt X86 has masked_load/store instruction in avx1 mode).
>
>
>
> Thanks everyone for the answers. My immediate motivation is to improve the
> masked load/store ops for an AVX target. If we can fix scatter/gather
> similarly, that would be great.
>
> Can we legalize the same set of masked load/store operations for AVX1 as
> AVX2? If I'm understanding them correctly, the AVX1 FP instructions
> (vmaskmovps/pd) can be used in place of the AVX2 int instructions
> (vpmaskmovd/q), just with domain crossing penalties thrown in. I think we
> do this for other missing integer ops for an AVX1 target either in x86
> lowering or in the tablegen patterns.
>
> Elena - I'm not too familiar with the vectorizers or scatter/gather,
but
> I'll certainly take a look at D15690. Thanks for pointing out the
patch!
>
>
>
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