llvm dev - Jan 2016 - a bundle with one instruction

You can have
>
> BUNDLE          // 2 instructions in a bundle
>   instruction1  //
>   instruction2  //
> instruction3    // single, non-bundled instruction
> BUNDLE          // another bundle with 2 instructions
>   instruction4  //
>   instruction5  //
>
> instruction3 is not bundled with anything, and it's between two other
> bundles---that's what I meant by "mixing".
>
>
> On Hexagon, on the hardware level, every instruction belongs to some
> packet, whether it's a packet with one or more instructions.  What we
do is
> that we encode single instructions as single-instruction packets, but that
> happens after the IR is lowered to the MC form.
>
>
> -Krzysztof
>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
>
Just to clarify, when you say MC form do you mean Hexagon Assembly?
Apologies if the question seems silly. I've been working with LLVM only a
few months.


-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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On 1/21/2016 4:53 PM, Rail Shafigulin wrote:
>
> Just to clarify, when you say MC form do you mean Hexagon Assembly?
> Apologies if the question seems silly. I've been working with LLVM only
> a few months.
No problem.  At some point the machine instructions represented by a 
class "MachineInstr" are transformed into a representation using class
"MCInst".  This is the MC level I'm talking about.  It's the 
representation that the llvm-mc uses.

-Krzysztof

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
hosted by The Linux Foundation

>
> No problem.  At some point the machine instructions represented by a class
> "MachineInstr" are transformed into a representation using class
"MCInst".
> This is the MC level I'm talking about.  It's the representation
that the
> llvm-mc uses.
>
>
Do you mind pointing out where in the code this is happening?


-- 
Rail Shafigulin
Software Engineer
Esencia Technologies

On Fri, Jan 22, 2016 at 6:35 AM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> On 1/21/2016 4:53 PM, Rail Shafigulin wrote:
>
>>
>> Just to clarify, when you say MC form do you mean Hexagon Assembly?
>> Apologies if the question seems silly. I've been working with LLVM
only
>> a few months.
>>
>
> No problem.  At some point the machine instructions represented by a class
> "MachineInstr" are transformed into a representation using class
"MCInst".
> This is the MC level I'm talking about.  It's the representation
that the
> llvm-mc uses.
>
>
> -Krzysztof
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
>


-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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