llvm dev - Jan 2016 - DFAPacketizer, Scheduling and LoadLatency

On Tue, Nov 17, 2015 at 11:15 AM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> On 11/17/2015 12:26 PM, Rail Shafigulin wrote:
>
>>
>> I tried setting
>> let mayLoad = 1 {
>>    class InstrLD .... {
>>     }
>> }
>>
>> But that didn't seem to work. When I looked at the debug output the
>> latency for the load instruction was set to 1.
>>
>> However when I changed load itinerary description in the schedule to
>>
>> def MyTargetItineraries :
>>      ..............
>>      InstrItinData<LD, [InstrStage<2, [BranchSlot,
NonBranchSlot], 1>]>,
>>      ..............
>>
>> That seem to produce correct latency in the debug output.
>>
>> Do you know what could be the problem? Am I missing something? To give
>> you a full disclosure, I'm using LLVM 3.5 and at the moment I
can't
>> switch to the latest version.
>>
>> Any help is appreciated.
>>
>
> I think that the LoadLatency is used as a last resort when there is no
> itinerary available for a given instruction.  In your case, there is one
> and so the LoadLatency is ignored, and instead the latency from the
> itinerary is used.
>
>
> -Krzysztof
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
>
I had a chance to test this and I'm somewhat confused. Earlier we concluded
that the connection between LoadLatency and a given instruction is through
mayLoad variable. In other words an instruction will set its latency value
to LoadLatency if mayLoad is set to 1. However this doesn't seem to be
happening in my case.

Here is my load instruction definition:

class InstLD<bits<4> op, dag outs, dag ins, string asmstr,
list<dag>
pattern>
  : InstEscala<outs, ins, asmstr, pattern> {
  let optype = 0b10;
  let opcode = op;
}

class LOAD<bits<4> subop, string asmstring, list<dag> pattern>
  : InstLD<subop, (outs GPR:$rD), (ins MEMri:$src),
           !strconcat(asmstring, "\t$rD, $src"), pattern> {
  bits<5> rD;
  bits<21> src;

  let Inst{25-21} = rD;
  let Inst{20-0} = src;
}

class LOADi32<bits<4> subop, string asmstring, PatFrag opNode>
  : LOAD<subop, asmstring, [(set (i32 GPR:$rD), (opNode ADDRri:$src))]>;

let Itinerary = l_lwz in
  def LWZ : LOADi32<0x1, "l.lwz", load>;

My instruction itinerary data looks like the following

InstrItinData<l_lwz    , [InstrStage<1, [Slot0, Slot1]>]>,

and my LoadLatency is set to 2.

As you can see mayLoad is never really set to 1 anywhere however it still
seems to be using a LoadLatency of 2. What am I missing?

Any help is appreciated.

-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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On 1/6/2016 1:59 PM, Rail Shafigulin wrote:
>
>
> let Itinerary = l_lwz in
>    def LWZ : LOADi32<0x1, "l.lwz", load>;
>
> My instruction itinerary data looks like the following
>
> InstrItinData<l_lwz    , [InstrStage<1, [Slot0, Slot1]>]>,
>
> and my LoadLatency is set to 2.
>
> As you can see mayLoad is never really set to 1 anywhere however it
> still seems to be using a LoadLatency of 2. What am I missing?

I'm not sure exactly what's going on in your case.  You can try to see 
if this is the function that causes the "2" to be returned.

unsigned TargetInstrInfo::
getInstrLatency(const InstrItineraryData *ItinData,
                 const MachineInstr *MI,
                 unsigned *PredCost) const {
   // Default to one cycle for no itinerary. However, an "empty" 
itinerary may
   // still have a MinLatency property, which getStageLatency checks.
   if (!ItinData)
     return MI->mayLoad() ? 2 : 1;

   return ItinData->getStageLatency(MI->getDesc().getSchedClass());
}


-Krzysztof


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
hosted by The Linux Foundation

>
> I'm not sure exactly what's going on in your case.  You can try to
see if
> this is the function that causes the "2" to be returned.
>
> unsigned TargetInstrInfo::
> getInstrLatency(const InstrItineraryData *ItinData,
>                 const MachineInstr *MI,
>                 unsigned *PredCost) const {
>   // Default to one cycle for no itinerary. However, an "empty"
itinerary
> may
>   // still have a MinLatency property, which getStageLatency checks.
>   if (!ItinData)
>     return MI->mayLoad() ? 2 : 1;
>
>   return ItinData->getStageLatency(MI->getDesc().getSchedClass());
>
> }
>
>
> -Krzysztof
>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
>
That's exactly it. Thanks for the explanation!

-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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