llvm dev - Dec 2015 - get instruction destination register

Dear Tim,
Thank you for your thorough reply. So, based on your reply I get every
operand and check them to be (isDef && !isimplicit). Now my problem is
that
it gives me the physical register number.i.e, for example, instead of r0,
it return %physreg66. Could you please help me on how to convert these
physical register number to the ARM related register? I mean the 15 GPRs in
ARM.
Thank you,
Fami

On Sat, Dec 19, 2015 at 5:02 PM, Tim Northover <t.p.northover at
gmail.com>
wrote:
> Hi Fami,
>
> On 19 December 2015 at 11:34, fateme Hoseini via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
> > I get my machine instruction, but I don't know how to get dest
reg. I
> looked
> > at MachineInstr.h but couldn't find it out.
>
> You probably want to iterate through the instruction's operands
> (MachineInstr::operands_begin/end) looking for defines ("isDef")
of
> the registers you care about. Some instructions will write multiple
> registers (e.g. ldrd), and the information is in a certain sense
> approximate (an empty inline asm block may be marked as writing some
> registers, but not actually do anything).
>
> A call instruction "BL" also gets marked with the registers the
> function uses for return values so that LLVM can track data-flow. You
> may or may not want that, if not then looking for non-implicit
> (!isImplicit) defines might be a better approximation.
>
> Finally, you probably have to be aware of subregisters even for GPRs,
> the ARM-mode ldrd instructions can only take sequential pairs, which
> LLVM models as a separate register called something like R0_R1.
>
> > Also I want to know which instructions to excluse from this routine,
for
> > example str instruction does not write to a dest reg or branch
> instruction.
>
> That's why you should check isDef for the ones you're after.
>
> Cheers.
>
> Tim.
>
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On 21 December 2015 at 13:24, fateme Hoseini <hoseini.f at gmail.com>
wrote:
> Thank you for your thorough reply. So, based on your reply I get every
> operand and check them to be (isDef && !isimplicit). Now my problem
is that
> it gives me the physical register number.i.e, for example, instead of r0,
it
> return %physreg66. Could you please help me on how to convert these
physical
> register number to the ARM related register? I mean the 15 GPRs in ARM.
You should be able to compare them to the generated enum:
"Op->getReg() == ARM::R0" for example. Alternatively you could use
"MCRegisterInfo::getEncodingValue" on "Op->getReg()",
which would
return 0-15 for the basic registers.

Cheers.

Tim.

Thank you so much.
I want to use ARM::R0, because I'm going to need this style for evaluating
opcodes as well. Forgive me if this is a stupid question question, but I
don't know how to include this information in my code. I think I have to
include "ARMBaseInfo.h", and
#include "../lib/Target/ARM/ARMBaseInfo.h" does not work!


On Mon, Dec 21, 2015 at 7:29 PM, Tim Northover <t.p.northover at
gmail.com>
wrote:
> On 21 December 2015 at 13:24, fateme Hoseini <hoseini.f at gmail.com>
wrote:
> > Thank you for your thorough reply. So, based on your reply I get every
> > operand and check them to be (isDef && !isimplicit). Now my
problem is
> that
> > it gives me the physical register number.i.e, for example, instead of
> r0, it
> > return %physreg66. Could you please help me on how to convert these
> physical
> > register number to the ARM related register? I mean the 15 GPRs in
ARM.
>
> You should be able to compare them to the generated enum:
> "Op->getReg() == ARM::R0" for example. Alternatively you could
use
> "MCRegisterInfo::getEncodingValue" on
"Op->getReg()", which would
> return 0-15 for the basic registers.
>
> Cheers.
>
> Tim.
>
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