llvm dev - Jan 2015 - [LLVMdev] [ARM, AArch64 backend] query regarding alias instructions

Hi All,
1. What are the various benefits of concept of alias instructions?
2. Could someone explain the benefit w.r.t CSET instruction in aarch64
CSET
Conditional set : Rd = if cond then 1 else 0
This instruction is an alias of the CSINC instruction.

3. Is handcoding of the instruction encoding and running -disassemble on llvm-mc
the only way to detect the correctness of the aliases provided?
    like in the testcases provided at \llvm\test\MC\Disassembler\AArch64

Regards,
Jyoti Allur

On Thu, Jan 8, 2015 at 11:55 PM, Jyoti Rajendra Allur <
jyoti.allur at samsung.com> wrote:
> Hi All,
> 1. What are the various benefits of concept of alias instructions?
>
In (mostly) older computers with variable length instructions and
microcoding there are often instructions such as MOV, MOVN, CLR, INC, DEC,
NOP that are shorter than and run faster than more general instructions
that achieve the same effect e.g. XOR a register with itself, or add or
subtract a literal 0 or 1, or -1.

On machines with longer, fixed length, encodings which execute almost every
instruction in the same amount of time there is no point to such special
instructions, but programmers are used to them, and it makes programs
clearer to explicitly say for example CLR x rather than XOR x,x. ANd so
manufacturers (or sometimes assembler authors) specify a pseudo-instruction
that is a special case of another instruction.

Sometimes there is more than one way to achieve the same effect (e.g. add
0, subtract 0, AND with 1, OR with 0, XOR with 0, shift by 0, branch never
are all possible alias expansions for NOP) so the manufacturer will specify
a particular one as the preferred alias, to ensure that disassembling and
then assembling a program produces the same result.

Other examples include powerful bitfield insert and extract instructions on
PowerPC that can be used to obtain the effect of simple logical shift and
rotate instructions on other ISAs.


> 2. Could someone explain the benefit w.r.t CSET instruction in aarch64
> CSET
> Conditional set : Rd = if cond then 1 else 0
> This instruction is an alias of the CSINC instruction.
>
The various conditional move instructions have the general encoding...

sf:1 op:1 "011010100" Rm:5 cond:4 "0" o2:1 Rn:5 Rd:5

.. and perform ...

if (cond){
  result = Rn;
} else {
  result = Rm;
  if(op) result = ~result;
  if(o2) result = result + 1;
}
Rd = result;

(sf determines whether it operates on 32 bit or 64 bit registers)

This can do a lot of different things, depending on whether op and o2 are 0
or 1, and whether one of the operands selects the Zero Register (register
31).

CSET is the special case where op = 0 (don't invert Rm), o2 = 1 (add 1 to
Rm), and Rn and Rm are both the Zero Register, so the result is either 0 or
0+1 = 1, depending on the condition.
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