The IMM3/IMM5 come from here X86RecognizableInstr.cpp 943 TYPE("SSECC", TYPE_IMM3) 944: TYPE("AVXCC", TYPE_IMM5) On Thu, Dec 25, 2014 at 8:22 PM, Jun Koi <junkoi2004 at gmail.com> wrote:> > > On Fri, Dec 26, 2014 at 11:54 AM, Jun Koi <junkoi2004 at gmail.com> wrote: > >> hi, >> >> some instructions mismatch between assembler & disassembler, like below. >> it seems this happens with all SSECC related instructions? >> >> thanks, >> Jun >> >> >> >> $ echo "cmpps xmm1, xmm2, 23" | ./Release+Asserts/bin/llvm-mc -assemble >> -triple=x86_64 --output-asm-variant=1 -x86-asm-syntax=intel -show-encoding >> .text >> cmpps xmm1, xmm2, 23 # encoding: [0x0f,0xc2,0xca,0x17] >> >> >> $ echo "0x0f,0xc2,0xca,0x17"|./Release+Asserts/bin/llvm-mc -disassemble >> -triple=x86_64 --output-asm-variant=1 >> .text >> <stdin>:1:1: warning: invalid instruction encoding >> 0x0f,0xc2,0xca,0x17 >> > > i am trying to figure out why this bug happens. according to the code in > X86DisassemblerDecoder.cpp, the last operand of CMPSS is checked against > TYPE_IMM5 (to be in the range [0, 31]), but i cannot find this TYPE_IMM5 > value anywhere in the definition of CMPSS, as below. > can somebody please enlighten me? > > thanks! > > // sse12_cmp_packed - sse 1 & 2 compare packed instructions > multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop, > Operand CC, Intrinsic Int, string asm, > string asm_alt, Domain d, > OpndItins itins = SSE_ALU_F32P> { > def rri : PIi8<0xC2, MRMSrcReg, > (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, > [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], > itins.rr, d>, > Sched<[WriteFAdd]>; > def rmi : PIi8<0xC2, MRMSrcMem, > (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, > [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], > itins.rm, d>, > Sched<[WriteFAddLd, ReadAfterLd]>; > > // Accept explicit immediate argument form instead of comparison code. > let isAsmParserOnly = 1, hasSideEffects = 0 in { > def rri_alt : PIi8<0xC2, MRMSrcReg, > (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), > asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>; > def rmi_alt : PIi8<0xC2, MRMSrcMem, > (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc), > asm_alt, [], itins.rm, d>, > Sched<[WriteFAddLd, ReadAfterLd]>; > } > } > > > let Constraints = "$src1 = $dst" in > { > defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, > int_x86_sse_cmp_ps, > "cmp${cc}ps\t{$src2, $dst|$dst, > $src2}", > "cmpps\t{$cc, $src2, $dst|$dst, $src2, > $cc}", > SSEPackedSingle, SSE_ALU_F32P>, > PS; > defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, > int_x86_sse2_cmp_pd, > "cmp${cc}pd\t{$src2, $dst|$dst, > $src2}", > "cmppd\t{$cc, $src2, $dst|$dst, $src2, > $cc}", > SSEPackedDouble, SSE_ALU_F64P>, > PD; > } > > > > >-- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20141225/1f27ce09/attachment.html>
Fixed in r224846 On Thu, Dec 25, 2014 at 8:58 PM, Craig Topper <craig.topper at gmail.com> wrote:> The IMM3/IMM5 come from here > > X86RecognizableInstr.cpp > > 943 TYPE("SSECC", TYPE_IMM3) > > 944: TYPE("AVXCC", TYPE_IMM5) > > On Thu, Dec 25, 2014 at 8:22 PM, Jun Koi <junkoi2004 at gmail.com> wrote: > >> >> >> On Fri, Dec 26, 2014 at 11:54 AM, Jun Koi <junkoi2004 at gmail.com> wrote: >> >>> hi, >>> >>> some instructions mismatch between assembler & disassembler, like below. >>> it seems this happens with all SSECC related instructions? >>> >>> thanks, >>> Jun >>> >>> >>> >>> $ echo "cmpps xmm1, xmm2, 23" | ./Release+Asserts/bin/llvm-mc -assemble >>> -triple=x86_64 --output-asm-variant=1 -x86-asm-syntax=intel -show-encoding >>> .text >>> cmpps xmm1, xmm2, 23 # encoding: [0x0f,0xc2,0xca,0x17] >>> >>> >>> $ echo "0x0f,0xc2,0xca,0x17"|./Release+Asserts/bin/llvm-mc -disassemble >>> -triple=x86_64 --output-asm-variant=1 >>> .text >>> <stdin>:1:1: warning: invalid instruction encoding >>> 0x0f,0xc2,0xca,0x17 >>> >> >> i am trying to figure out why this bug happens. according to the code in >> X86DisassemblerDecoder.cpp, the last operand of CMPSS is checked against >> TYPE_IMM5 (to be in the range [0, 31]), but i cannot find this TYPE_IMM5 >> value anywhere in the definition of CMPSS, as below. >> can somebody please enlighten me? >> >> thanks! >> >> // sse12_cmp_packed - sse 1 & 2 compare packed instructions >> multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop, >> Operand CC, Intrinsic Int, string asm, >> string asm_alt, Domain d, >> OpndItins itins = SSE_ALU_F32P> { >> def rri : PIi8<0xC2, MRMSrcReg, >> (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, >> [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], >> itins.rr, d>, >> Sched<[WriteFAdd]>; >> def rmi : PIi8<0xC2, MRMSrcMem, >> (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, >> [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], >> itins.rm, d>, >> Sched<[WriteFAddLd, ReadAfterLd]>; >> >> // Accept explicit immediate argument form instead of comparison code. >> let isAsmParserOnly = 1, hasSideEffects = 0 in { >> def rri_alt : PIi8<0xC2, MRMSrcReg, >> (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), >> asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>; >> def rmi_alt : PIi8<0xC2, MRMSrcMem, >> (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc), >> asm_alt, [], itins.rm, d>, >> Sched<[WriteFAddLd, ReadAfterLd]>; >> } >> } >> >> >> let Constraints = "$src1 = $dst" in >> { >> defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, >> int_x86_sse_cmp_ps, >> "cmp${cc}ps\t{$src2, $dst|$dst, >> $src2}", >> "cmpps\t{$cc, $src2, $dst|$dst, $src2, >> $cc}", >> SSEPackedSingle, SSE_ALU_F32P>, >> PS; >> defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, >> int_x86_sse2_cmp_pd, >> "cmp${cc}pd\t{$src2, $dst|$dst, >> $src2}", >> "cmppd\t{$cc, $src2, $dst|$dst, $src2, >> $cc}", >> SSEPackedDouble, SSE_ALU_F64P>, >> PD; >> } >> >> >> >> >> > > > -- > ~Craig >-- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20141225/24722964/attachment.html>
nice work, thanks! On Fri, Dec 26, 2014 at 2:37 PM, Craig Topper <craig.topper at gmail.com> wrote:> Fixed in r224846 > > On Thu, Dec 25, 2014 at 8:58 PM, Craig Topper <craig.topper at gmail.com> > wrote: > >> The IMM3/IMM5 come from here >> >> X86RecognizableInstr.cpp >> >> 943 TYPE("SSECC", TYPE_IMM3) >> >> 944: TYPE("AVXCC", TYPE_IMM5) >> >> On Thu, Dec 25, 2014 at 8:22 PM, Jun Koi <junkoi2004 at gmail.com> wrote: >> >>> >>> >>> On Fri, Dec 26, 2014 at 11:54 AM, Jun Koi <junkoi2004 at gmail.com> wrote: >>> >>>> hi, >>>> >>>> some instructions mismatch between assembler & disassembler, like below. >>>> it seems this happens with all SSECC related instructions? >>>> >>>> thanks, >>>> Jun >>>> >>>> >>>> >>>> $ echo "cmpps xmm1, xmm2, 23" | ./Release+Asserts/bin/llvm-mc -assemble >>>> -triple=x86_64 --output-asm-variant=1 -x86-asm-syntax=intel -show-encoding >>>> .text >>>> cmpps xmm1, xmm2, 23 # encoding: [0x0f,0xc2,0xca,0x17] >>>> >>>> >>>> $ echo "0x0f,0xc2,0xca,0x17"|./Release+Asserts/bin/llvm-mc -disassemble >>>> -triple=x86_64 --output-asm-variant=1 >>>> .text >>>> <stdin>:1:1: warning: invalid instruction encoding >>>> 0x0f,0xc2,0xca,0x17 >>>> >>> >>> i am trying to figure out why this bug happens. according to the code in >>> X86DisassemblerDecoder.cpp, the last operand of CMPSS is checked against >>> TYPE_IMM5 (to be in the range [0, 31]), but i cannot find this TYPE_IMM5 >>> value anywhere in the definition of CMPSS, as below. >>> can somebody please enlighten me? >>> >>> thanks! >>> >>> // sse12_cmp_packed - sse 1 & 2 compare packed instructions >>> multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop, >>> Operand CC, Intrinsic Int, string asm, >>> string asm_alt, Domain d, >>> OpndItins itins = SSE_ALU_F32P> { >>> def rri : PIi8<0xC2, MRMSrcReg, >>> (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, >>> [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], >>> itins.rr, d>, >>> Sched<[WriteFAdd]>; >>> def rmi : PIi8<0xC2, MRMSrcMem, >>> (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, >>> [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), >>> imm:$cc))], >>> itins.rm, d>, >>> Sched<[WriteFAddLd, ReadAfterLd]>; >>> >>> // Accept explicit immediate argument form instead of comparison code. >>> let isAsmParserOnly = 1, hasSideEffects = 0 in { >>> def rri_alt : PIi8<0xC2, MRMSrcReg, >>> (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), >>> asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>; >>> def rmi_alt : PIi8<0xC2, MRMSrcMem, >>> (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc), >>> asm_alt, [], itins.rm, d>, >>> Sched<[WriteFAddLd, ReadAfterLd]>; >>> } >>> } >>> >>> >>> let Constraints = "$src1 = $dst" in >>> { >>> defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, >>> int_x86_sse_cmp_ps, >>> "cmp${cc}ps\t{$src2, $dst|$dst, >>> $src2}", >>> "cmpps\t{$cc, $src2, $dst|$dst, $src2, >>> $cc}", >>> SSEPackedSingle, SSE_ALU_F32P>, >>> PS; >>> defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, >>> int_x86_sse2_cmp_pd, >>> "cmp${cc}pd\t{$src2, $dst|$dst, >>> $src2}", >>> "cmppd\t{$cc, $src2, $dst|$dst, $src2, >>> $cc}", >>> SSEPackedDouble, SSE_ALU_F64P>, >>> PD; >>> } >>> >>> >>> >>> >>> >> >> >> -- >> ~Craig >> > > > > -- > ~Craig >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20141226/64511fbc/attachment.html>