MAYUR PANDEY
2014-Nov-24 15:00 UTC
[LLVMdev] bx instruction getting generated in arm assembly for O1
<HTML><HEAD><TITLE>Samsung Enterprise Portal mySingle</TITLE> <META content=IE=5 http-equiv=X-UA-Compatible> <META content="text/html; charset=utf-8" http-equiv=Content-Type> <STYLE id=mysingle_style type=text/css>P { MARGIN-BOTTOM: 5px; FONT-SIZE: 9pt; FONT-FAMILY: Arial, arial; MARGIN-TOP: 5px } TD { MARGIN-BOTTOM: 5px; FONT-SIZE: 9pt; FONT-FAMILY: Arial, arial; MARGIN-TOP: 5px } LI { MARGIN-BOTTOM: 5px; FONT-SIZE: 9pt; FONT-FAMILY: Arial, arial; MARGIN-TOP: 5px } BODY { FONT-SIZE: 9pt; FONT-FAMILY: Arial, arial; MARGIN: 10px; LINE-HEIGHT: 1.4 } </STYLE> <META name=GENERATOR content=ActiveSquare></HEAD> <BODY> <META name=GENERATOR content=ActiveSquare> <P>Hi,</P> <P> </P> <P>For the following test:</P> <P>int (*indirect_func)();</P> <P>int indirect_call()<BR>{<BR> return indirect_func();<BR>}</P> <P> </P> <P>when generating the assembly with clang-3.5, for -march=armv5te, there is a difference in the assemblies generated with O0 and O1:</P> <P> </P> <P>In the assembly generated with O0, we are getting the "blx" instruction whereas with O1 we get "bx" (in 3.4.2 we used to get "blx" for both O0 and O1). </P> <P> </P> <P>Is this because of this patch: [llvm] r214959 - ARM: do not generate BLX instructions on Cortex-M CPUs</P> <P>Or I am missing something.</P> <P> </P> <P>Thanks,</P> <P>Mayur</P> <H2 tabIndex=-1 id=:3gi class=hP> </H2><!--SP:mayur.p--><!--mayur.p:EP--> <P> </P></BODY></HTML><img src='http://ext.samsung.net/mailcheck/SeenTimeChecker?do=e3e1a57eba32dd3d704a2e0b00311e332e8c5dc67bebec10f294c62af3385af4958dbbabe087ac9c0029dc535ebebcd3326bbdfb2ea96a2fcf878f9a26ce15a0' border=0 width=0 height=0 style='display:none'>
Jonathan Roelofs
2014-Nov-25 01:15 UTC
[LLVMdev] bx instruction getting generated in arm assembly for O1
On 11/24/14 8:00 AM, MAYUR PANDEY wrote:> Hi, > > For the following test: > > int (*indirect_func)(); > > int indirect_call() > { > return indirect_func(); > } > > when generating the assembly with clang-3.5, for -march=armv5te, there is a > difference in the assemblies generated with O0 and O1: > > In the assembly generated with O0, we are getting the "blx" instruction whereas > with O1 we get "bx" (in 3.4.2 we used to get "blx" for both O0 and O1).Can you post the asm that you're seeing for this function? There's a related case to this on armv4t which Iain has a patch for, that I think we forgot about... The problem there is that armv4t doesn't have blx at all, so should be generating a sequence like: 'mov r0, ...; bx _Ltmp; _Ltmp: bl r0'.> > Is this because of this patch: [llvm] r214959 - ARM: do not generate BLX > instructions on Cortex-M CPUsI doubt it. armv5te isn't a cortex-m processor. Cheers, Jon> > Or I am missing something. > > Thanks, > > Mayur > > > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >-- Jon Roelofs jonathan at codesourcery.com CodeSourcery / Mentor Embedded
David Chisnall
2014-Nov-25 09:27 UTC
[LLVMdev] bx instruction getting generated in arm assembly for O1
On 24 Nov 2014, at 15:00, MAYUR PANDEY <mayur.p at samsung.com> wrote:> int (*indirect_func)(); > int indirect_call() > { > return indirect_func(); > } > > when generating the assembly with clang-3.5, for -march=armv5te, there is a difference in the assemblies generated with O0 and O1: > > In the assembly generated with O0, we are getting the "blx" instruction whereas with O1 we get "bx" (in 3.4.2 we used to get "blx" for both O0 and O1).I'm a bit confused about what you think that you're testing - that's exactly what I'd expect to see. Without optimisation, the call will be a blx (call) followed by a function epilog. With optimisation, as the result of the callee is returned in the same register as the caller, it is a tail call, so a simple branch (bx - as you don't know at compile time whether it's a branch to ARM or Thumb code) should be emitted. David