>> // Increment loop variable and jmp >> BuildMI(*MBB_erase, MBB_erase->end(), db, >> TII->get(X86::ADD64ri32),reg).addReg(reg).addImm(8);>> It looks like this instruction is defining virtual register "reg" the second time.Thx for your answer... Why would it define it again? I just want to use this register and add something to it... Cheers
I was just pointing out that "reg" is defined by two instructions, which shouldn't happen when the code is still in SSA. "reg" is first defined by phi, // Update phi node BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::PHI), reg).addReg(reg).addMBB(MBB). ... and defined again by this instruction: BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::ADD64ri32), reg).addReg(reg).addImm(8); On Wed, Oct 29, 2014 at 3:07 AM, Rinaldini Julien < julien.rinaldini at heig-vd.ch> wrote:> >> // Increment loop variable and jmp > >> BuildMI(*MBB_erase, MBB_erase->end(), db, >> > TII->get(X86::ADD64ri32),reg).addReg(reg).addImm(8); > > > > > > It looks like this instruction is defining virtual register "reg" the > second time. > > Thx for your answer... > Why would it define it again? I just want to use this register and add > something to it... > > Cheers >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20141029/b41e6e06/attachment.html>
Ok, I have to maintain the SSA form... Thx for your help Cheers On 10/29/2014 05:49 PM, Akira Hatanaka wrote:> I was just pointing out that "reg" is defined by two instructions, which > shouldn't happen when the code is still in SSA. > > "reg" is first defined by phi, > // Update phi node > BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::PHI), > reg).addReg(reg).addMBB(MBB). > ... > > and defined again by this instruction: > > BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::ADD64ri32), > reg).addReg(reg).addImm(8); > > On Wed, Oct 29, 2014 at 3:07 AM, Rinaldini Julien < > julien.rinaldini at heig-vd.ch> wrote: > >>>> // Increment loop variable and jmp >>>> BuildMI(*MBB_erase, MBB_erase->end(), db, >> >> TII->get(X86::ADD64ri32),reg).addReg(reg).addImm(8); >> >>> >> >>> It looks like this instruction is defining virtual register "reg" the >> second time. >> >> Thx for your answer... >> Why would it define it again? I just want to use this register and add >> something to it... >> >> Cheers >> >