Hi, The x86 CPU IMUL instruction has forms such as: IMUL reg EDX:EAX ← EAX ∗ reg reg, EAX and EDX are 32bit registers. How can I represent this sort of instruction in LLVM IR ? It is really a 32bit * 32 bit = 64 bit, but no LLVM IR exists to do that. Or, a similar question: What LLVM IR would produce this IMUL instruction form? For context, I am writing a x86 to LLVM IR decompiler, so wish to represent IMUL in LLVM IR. Kind Regards James
> For context, I am writing a x86 to LLVM IR decompiler, so wish to > represent IMUL in LLVM IR.>From a decompiler's perspective, it probably represents 3instructions: 2 sexts (imul is the signed one, isn't it?) and a mul. With the usual caveats you'll be dealing with over EFLAGS. Cheers. Tim.
On Jul 13, 2014 5:57 PM, "Tim Northover" <t.p.northover at gmail.com> wrote:> > > For context, I am writing a x86 to LLVM IR decompiler, so wish to > > represent IMUL in LLVM IR. > > From a decompiler's perspective, it probably represents 3 > instructions: 2 sexts (imul is the signed one, isn't it?) and a mul. > With the usual caveats you'll be dealing with over EFLAGS. >I will take a bit more than that, if the following instructions only use edx. Are there any llvm ir instructions that can break a 64bit value into 2 32bit values. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140713/13520fb5/attachment.html>