Daniel Sanders
2014-Jul-09 10:45 UTC
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
The documentation for MSA can be found at
http://www.imgtec.com/mips/architectures/simd.asp. MSA was added to the
architecture fairly recently and the P5600
(http://www.imgtec.com/mips/warrior/pclass.asp) is the first core to support it.
For the implementation, search for 'addMSAFloatType(MVT::v8f16,
&Mips::MSA128HRegClass);' in lib/Target/Mips/MipsSEISelLowering.cpp.
Most operations are expanded but it supports ISD::LOAD, ISD::STORE,
ISD::BITCAST, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, BUILD_VECTOR, and
a couple intrinsics. In MipsMSAInstrInto.td, you can also search for FEXDO_H,
FEXUPL_W, and FEXUPR_W which are the only operations that use v8f16. There is no
reference to the 'f16' type in the Mips backend so scalars are not
implemented.
From: yalong at multicorewareinc.com [mailto:yalong at multicorewareinc.com]
Sent: 10 July 2014 01:49
To: Daniel Sanders; Kevin Qin
Cc: llvmdev
Subject: Re: RE: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select:
0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
Hi Daniel,
Thank you your replying.
Yes, the problem is about MIPS backend. You give me this message
"There is limited support for the <8 x f16> type when MSA (MIPS SIMD
Architecture) is enabled but even then scalar half-precision is not currently
supported." Could you give me some official link or some evidence? Thank
you very much.
Robin
________________________________
yalong at multicorewareinc.com<mailto:yalong at multicorewareinc.com>
From: Daniel Sanders<mailto:Daniel.Sanders at imgtec.com>
Date: 2014-07-09 02:05
To: yalong at multicorewareinc.com<mailto:yalong at multicorewareinc.com>;
Kevin Qin<mailto:kevinqindev at gmail.com>
CC: llvmdev<mailto:llvmdev at cs.uiuc.edu>
Subject: RE: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select:
0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
Hi,
NEON is an ARM feature and is therefore not supported by MIPS so I assume you
are trying to achieve the same effect. As far as I know, the MIPS backend
doesn't support half-precision floating point at the moment.
There is limited support for the <8 x f16> type when MSA (MIPS SIMD
Architecture) is enabled but even then scalar half-precision is not currently
supported.
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of yalong at multicorewareinc.com
Sent: 09 July 2014 23:31
To: Kevin Qin
Cc: llvmdev
Subject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select:
0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
Thank you Kevin!!!
If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, "fptrunc
double %tmp to float" is right, but "fptrunc float %tmp to half"
is wrong). My target platform is MIPS. The command as following:
NEON:
vcvtt.f16.f32 s2, s0
llvm Code:
%Vt_2 = load float* %VFP_s0, align 4
%Vt3_1 = fptrunc float %Vt_2 to half
%Vt4_1 = bitcast half %Vt3_1 to i16
%Vt2_2 = bitcast float* %VFP_s2 to <2 x i16>*
%Vrti_1 = load <2 x i16>* %Vt2_2, align 4
%Vrti_2 = insertelement <2 x i16> %Vrti_1, i16 %Vt4_1, i32 1
%Vt2_3 = bitcast float* %VFP_s2 to <2 x i16>*
store <2 x i16> %Vrti_2, <2 x i16>* %Vt2_3, align 4
Error Log:
LLVM ERROR: Cannot select: 0x9f554b0: ch = store 0x9d0f28c, 0x9f5d900,
0x9f54ba8, 0x9f54b20<ST2[FixedStack0](align=4), trunc to f16> [ID=52]
0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]>
[ORD=1810] [ID=51]
0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31]
0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26]
0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1]
0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
0x9f54ba8: i32 = FrameIndex<0> [ID=24]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
In function: testVCVTT32TO16Function
________________________________
yalong at multicorewareinc.com<mailto:yalong at multicorewareinc.com>
From: Kevin Qin<mailto:kevinqindev at gmail.com>
Date: 2014-07-09 00:03
To: yalong at multicorewareinc.com<mailto:yalong at multicorewareinc.com>
CC: llvmdev<mailto:llvmdev at cs.uiuc.edu>
Subject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select:
0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
Hi,
Can you show us the command line you are using? At least can you tell us the
backend you tried on? If you can upload the test case as well, it will be very
useful to find out the problem.
Regards,
Kevin
2014-07-10 1:53 GMT+08:00 yalong at multicorewareinc.com<mailto:yalong at
multicorewareinc.com> <yalong at multicorewareinc.com<mailto:yalong at
multicorewareinc.com>>:
Hi all,
I am new to llvm. I need help. Thank you every!
I want to realize vcvtt.f16.f32 NEON instruction by llvm. This instruction
covert top-16bits of a single type to f16. I use the intrinsics function
llvm.convert.to.fp16, but cannot llc , I meet is following problem :
LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16]
0x9fc0750: f32,ch = load 0x3aafd68, 0x9fc2a20,
0x9feaab0<LD4[%sunkaddr85033]> [ORD=125117] [ID=15]
0x9fc2a20: i32 = add 0x9fed880, 0x9fd9ea0 [ORD=125115] [ID=13]
0x9fed880: i32,ch = CopyFromReg 0x3aafd68, 0x9fbea90 [ORD=125114] [ID=9]
0x9fbea90: i32 = Register %vreg13999 [ORD=125114] [ID=1]
0x9fd9ea0: i32 = Constant<80> [ORD=125115] [ID=2]
0x9feaab0: i32 = undef [ORD=125117] [ID=4]
In function: internal_function_69
Command exited with non-zero status 1
If I change the method, I use " %1 = fptrunc float %0 to half ",
then " %2 = bitcast half %1 to i16", I meet samiliar problem, the log
is following:
LLVM ERROR: Cannot select: 0x9f554b0: ch = store 0x9d0f28c, 0x9f5d900,
0x9f54ba8, 0x9f54b20<ST2[FixedStack0](align=4), trunc to f16> [ID=52]
0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]>
[ORD=1810] [ID=51]
0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31]
0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26]
0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1]
0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
0x9f54ba8: i32 = FrameIndex<0> [ID=24]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
In function: testVCVTT32TO16Function
Anyone can help me?? Thank you again.
________________________________
yalong at multicorewareinc.com<mailto:yalong at multicorewareinc.com>
_______________________________________________
LLVM Developers mailing list
LLVMdev at cs.uiuc.edu<mailto:LLVMdev at cs.uiuc.edu>
http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
--
Best Regards,
Kevin Qin
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yalong at multicorewareinc.com
2014-Jul-10 00:49 UTC
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
Hi Daniel, Thank you your replying. Yes, the problem is about MIPS backend. You give me this message "There is limited support for the <8 x f16> type when MSA (MIPS SIMD Architecture) is enabled but even then scalar half-precision is not currently supported." Could you give me some official link or some evidence? Thank you very much. Robin yalong at multicorewareinc.com From: Daniel SandersDate: 2014-07-09 02:05To: yalong at multicorewareinc.com; Kevin QinCC: llvmdevSubject: RE: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!! Hi, NEON is an ARM feature and is therefore not supported by MIPS so I assume you are trying to achieve the same effect. As far as I know, the MIPS backend doesn't support half-precision floating point at the moment. There is limited support for the <8 x f16> type when MSA (MIPS SIMD Architecture) is enabled but even then scalar half-precision is not currently supported. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of yalong at multicorewareinc.com Sent: 09 July 2014 23:31 To: Kevin Qin Cc: llvmdev Subject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!! Thank you Kevin!!! If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, "fptrunc double %tmp to float" is right, but "fptrunc float %tmp to half" is wrong). My target platform is MIPS. The command as following: NEON: vcvtt.f16.f32 s2, s0 llvm Code: %Vt_2 = load float* %VFP_s0, align 4 %Vt3_1 = fptrunc float %Vt_2 to half %Vt4_1 = bitcast half %Vt3_1 to i16 %Vt2_2 = bitcast float* %VFP_s2 to <2 x i16>* %Vrti_1 = load <2 x i16>* %Vt2_2, align 4 %Vrti_2 = insertelement <2 x i16> %Vrti_1, i16 %Vt4_1, i32 1 %Vt2_3 = bitcast float* %VFP_s2 to <2 x i16>* store <2 x i16> %Vrti_2, <2 x i16>* %Vt2_3, align 4 Error Log: LLVM ERROR: Cannot select: 0x9f554b0: ch = store 0x9d0f28c, 0x9f5d900, 0x9f54ba8, 0x9f54b20<ST2[FixedStack0](align=4), trunc to f16> [ID=52] 0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51] 0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31] 0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26] 0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1] 0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17] 0x9f54b20: i32 = undef [ORD=1797] [ID=6] 0x9f54ba8: i32 = FrameIndex<0> [ID=24] 0x9f54b20: i32 = undef [ORD=1797] [ID=6] In function: testVCVTT32TO16Function yalong at multicorewareinc.com From: Kevin Qin Date: 2014-07-09 00:03 To: yalong at multicorewareinc.com CC: llvmdev Subject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!! Hi, Can you show us the command line you are using? At least can you tell us the backend you tried on? If you can upload the test case as well, it will be very useful to find out the problem. Regards, Kevin 2014-07-10 1:53 GMT+08:00 yalong at multicorewareinc.com <yalong at multicorewareinc.com>: Hi all, I am new to llvm. I need help. Thank you every! I want to realize vcvtt.f16.f32 NEON instruction by llvm. This instruction covert top-16bits of a single type to f16. I use the intrinsics function llvm.convert.to.fp16, but cannot llc , I meet is following problem : LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] 0x9fc0750: f32,ch = load 0x3aafd68, 0x9fc2a20, 0x9feaab0<LD4[%sunkaddr85033]> [ORD=125117] [ID=15] 0x9fc2a20: i32 = add 0x9fed880, 0x9fd9ea0 [ORD=125115] [ID=13] 0x9fed880: i32,ch = CopyFromReg 0x3aafd68, 0x9fbea90 [ORD=125114] [ID=9] 0x9fbea90: i32 = Register %vreg13999 [ORD=125114] [ID=1] 0x9fd9ea0: i32 = Constant<80> [ORD=125115] [ID=2] 0x9feaab0: i32 = undef [ORD=125117] [ID=4] In function: internal_function_69 Command exited with non-zero status 1 If I change the method, I use " %1 = fptrunc float %0 to half ", then " %2 = bitcast half %1 to i16", I meet samiliar problem, the log is following: LLVM ERROR: Cannot select: 0x9f554b0: ch = store 0x9d0f28c, 0x9f5d900, 0x9f54ba8, 0x9f54b20<ST2[FixedStack0](align=4), trunc to f16> [ID=52] 0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51] 0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31] 0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26] 0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1] 0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17] 0x9f54b20: i32 = undef [ORD=1797] [ID=6] 0x9f54ba8: i32 = FrameIndex<0> [ID=24] 0x9f54b20: i32 = undef [ORD=1797] [ID=6] In function: testVCVTT32TO16Function Anyone can help me?? Thank you again. yalong at multicorewareinc.com _______________________________________________ LLVM Developers mailing list LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev -- Best Regards, Kevin Qin -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140709/51fffa6a/attachment.html>
yalong at multicorewareinc.com
2014-Jul-10 22:34 UTC
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
Hi Daniel, Thank you give me important and useful help and information. Robin yalong at multicorewareinc.com From: Daniel SandersDate: 2014-07-09 03:45To: yalong at multicorewareinc.com; Kevin QinCC: llvmdevSubject: RE: RE: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!! The documentation for MSA can be found at http://www.imgtec.com/mips/architectures/simd.asp. MSA was added to the architecture fairly recently and the P5600 (http://www.imgtec.com/mips/warrior/pclass.asp) is the first core to support it. For the implementation, search for 'addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);' in lib/Target/Mips/MipsSEISelLowering.cpp. Most operations are expanded but it supports ISD::LOAD, ISD::STORE, ISD::BITCAST, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, BUILD_VECTOR, and a couple intrinsics. In MipsMSAInstrInto.td, you can also search for FEXDO_H, FEXUPL_W, and FEXUPR_W which are the only operations that use v8f16. There is no reference to the 'f16' type in the Mips backend so scalars are not implemented. From: yalong at multicorewareinc.com [mailto:yalong at multicorewareinc.com] Sent: 10 July 2014 01:49 To: Daniel Sanders; Kevin Qin Cc: llvmdev Subject: Re: RE: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!! Hi Daniel, Thank you your replying. Yes, the problem is about MIPS backend. You give me this message "There is limited support for the <8 x f16> type when MSA (MIPS SIMD Architecture) is enabled but even then scalar half-precision is not currently supported." Could you give me some official link or some evidence? Thank you very much. Robin yalong at multicorewareinc.com From: Daniel Sanders Date: 2014-07-09 02:05 To: yalong at multicorewareinc.com; Kevin Qin CC: llvmdev Subject: RE: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!! Hi, NEON is an ARM feature and is therefore not supported by MIPS so I assume you are trying to achieve the same effect. As far as I know, the MIPS backend doesn't support half-precision floating point at the moment. There is limited support for the <8 x f16> type when MSA (MIPS SIMD Architecture) is enabled but even then scalar half-precision is not currently supported. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of yalong at multicorewareinc.com Sent: 09 July 2014 23:31 To: Kevin Qin Cc: llvmdev Subject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!! Thank you Kevin!!! If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, "fptrunc double %tmp to float" is right, but "fptrunc float %tmp to half" is wrong). My target platform is MIPS. The command as following: NEON: vcvtt.f16.f32 s2, s0 llvm Code: %Vt_2 = load float* %VFP_s0, align 4 %Vt3_1 = fptrunc float %Vt_2 to half %Vt4_1 = bitcast half %Vt3_1 to i16 %Vt2_2 = bitcast float* %VFP_s2 to <2 x i16>* %Vrti_1 = load <2 x i16>* %Vt2_2, align 4 %Vrti_2 = insertelement <2 x i16> %Vrti_1, i16 %Vt4_1, i32 1 %Vt2_3 = bitcast float* %VFP_s2 to <2 x i16>* store <2 x i16> %Vrti_2, <2 x i16>* %Vt2_3, align 4 Error Log: LLVM ERROR: Cannot select: 0x9f554b0: ch = store 0x9d0f28c, 0x9f5d900, 0x9f54ba8, 0x9f54b20<ST2[FixedStack0](align=4), trunc to f16> [ID=52] 0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51] 0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31] 0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26] 0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1] 0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17] 0x9f54b20: i32 = undef [ORD=1797] [ID=6] 0x9f54ba8: i32 = FrameIndex<0> [ID=24] 0x9f54b20: i32 = undef [ORD=1797] [ID=6] In function: testVCVTT32TO16Function yalong at multicorewareinc.com From: Kevin Qin Date: 2014-07-09 00:03 To: yalong at multicorewareinc.com CC: llvmdev Subject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!! Hi, Can you show us the command line you are using? At least can you tell us the backend you tried on? If you can upload the test case as well, it will be very useful to find out the problem. Regards, Kevin 2014-07-10 1:53 GMT+08:00 yalong at multicorewareinc.com <yalong at multicorewareinc.com>: Hi all, I am new to llvm. I need help. Thank you every! I want to realize vcvtt.f16.f32 NEON instruction by llvm. This instruction covert top-16bits of a single type to f16. I use the intrinsics function llvm.convert.to.fp16, but cannot llc , I meet is following problem : LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] 0x9fc0750: f32,ch = load 0x3aafd68, 0x9fc2a20, 0x9feaab0<LD4[%sunkaddr85033]> [ORD=125117] [ID=15] 0x9fc2a20: i32 = add 0x9fed880, 0x9fd9ea0 [ORD=125115] [ID=13] 0x9fed880: i32,ch = CopyFromReg 0x3aafd68, 0x9fbea90 [ORD=125114] [ID=9] 0x9fbea90: i32 = Register %vreg13999 [ORD=125114] [ID=1] 0x9fd9ea0: i32 = Constant<80> [ORD=125115] [ID=2] 0x9feaab0: i32 = undef [ORD=125117] [ID=4] In function: internal_function_69 Command exited with non-zero status 1 If I change the method, I use " %1 = fptrunc float %0 to half ", then " %2 = bitcast half %1 to i16", I meet samiliar problem, the log is following: LLVM ERROR: Cannot select: 0x9f554b0: ch = store 0x9d0f28c, 0x9f5d900, 0x9f54ba8, 0x9f54b20<ST2[FixedStack0](align=4), trunc to f16> [ID=52] 0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51] 0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31] 0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26] 0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1] 0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17] 0x9f54b20: i32 = undef [ORD=1797] [ID=6] 0x9f54ba8: i32 = FrameIndex<0> [ID=24] 0x9f54b20: i32 = undef [ORD=1797] [ID=6] In function: testVCVTT32TO16Function Anyone can help me?? Thank you again. yalong at multicorewareinc.com _______________________________________________ LLVM Developers mailing list LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev -- Best Regards, Kevin Qin -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140710/23cc1648/attachment.html>