llvm dev - Jul 2014 - [LLVMdev] codeGen, instruction write one value to the input register.

Tks  Cameron, 

I did some study on it.

Now I am having the same problem as mentioned in this
thread;"http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-January/057654.html”
,
> Looking at the X86 back-end code, it looks like there do exist
> multi-output instructions, but they all use physical (implicit) registers
> for the second destination, not arbitrary register types.  And if I change
> the second destination to be a certain physical register, this problem goes
> away in my code.  Is this just not a supported case currently?  Or am I
> doing something wrong?
Wondering if there is any update about it?

best

kevin
On Jun 16, 2014, at 5:08 PM, Cameron McInally <cameron.mcinally at
nyu.edu> wrote:
> On Mon, Jun 16, 2014 at 4:51 PM, kewuzhang <kewu.zhang at amd.com>
wrote:
>> Hi Guys,
>> 
>> In  LLVM codegen,
>> a typical binary operation instruction is defined something like below:
>> 
>> "  def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a,
Int1Regs:$b),
>>          "xor.pred \t$dst, $a, $b;",
>>      [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
>> “
>> 
>> which takes two inputs and write the result to the $dst register.
>> 
>> Then how to define a binary instruction which returns two results, one
is
>> written to the $dst register, and the other one is written to one of
the
>> inputs? I mean, to implement something like:
>> ”
>> Type sincos( Type input,  Type * cosVal)
>> “
>> 
>> the instruction will compute sin and cos value of input, return the sin
>> result and write the cos result to cosVal.
>> Is there anything special constraints or something I should put onto
the cos
>> register?
>> 
> 
> Hey Kevin,
> 
> You might get a good start looking at the AVX2 VGATHER patterns in
> llvm/lib/Target/X86/X86InstrSSE.td. Those patterns return two results.
> They also make use of the @earlyclobber constraint.
> 
> Hope that helps,
> Cameron
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> Now I am having the same problem as mentioned in this
>
thread;"http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-January/057654.html”
>
> [...]
>
> Wondering if there is any update about it?
This has been a known issue since almost the beginning of LLVM from
what I've picked up (certainly long before I'd even heard of the
project). There hasn't been any progress since those messages, I'm
afraid: for two or more generic outputs you need C++ for ISel
(usually).

Cheers.

Tim.

Hi All, 

In XCore backend,  I saw 
“
…...
  EVT VT = Op.getValueType();
      SDValue Data         DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT,
VT),
                    Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3));
      SDValue Crc(Data.getNode(), 1);
      SDValue Results[] = { Crc, Data };
      return DAG.getMergeValues(Results, 2, DL);
“  which is used to lower an instruction that returns two values.

I am trying to something like this:
”
…….
SDValue z = DAG.getNode(my_ISD::test_op, DL, VT, Op.getOperand(0);
SDValue w = DAG.getConstant(1, MVT::i32);

SDValue DataZ = DAG.getNode(ISD::BUILDER_VECTOR, DL, MVT::v4i32, z, z, z, z);
SDValue DataW = DAG.getNode(ISD::BUILDER_VECTOR, DL, MVT::v4i32, w, w, w, w);
SDValue result[] = {DataZ, DataW};
return DAg.getMergeValues(results, 2, DL);

“
but my view-dag only shows one return value,  wondering what is wrong? 
should the results dags must be somehow “dependent” on each other?

Best

kevin

On Jul 7, 2014, at 2:54 PM, Tim Northover <t.p.northover at gmail.com>
wrote:
>> Now I am having the same problem as mentioned in this
>>
thread;"http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-January/057654.html”
>> 
>> [...]
>> 
>> Wondering if there is any update about it?
> 
> This has been a known issue since almost the beginning of LLVM from
> what I've picked up (certainly long before I'd even heard of the
> project). There hasn't been any progress since those messages, I'm
> afraid: for two or more generic outputs you need C++ for ISel
> (usually).
> 
> Cheers.
> 
> Tim.
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