llvm dev - Jun 2014 - [LLVMdev] Passing specific register for an Instruction in target description files.

Hi all,

I want to generate an assembly instruction for my target using target
description representation of the instruction. The problem is that I want to
add direct register to be chose as an output register for my target. Does it
possible to do with an instruction definition in TARGETInstrInfo.td  file? 
May be someone could help with an example?

Currently I have seen that we can pass the name of the registers' group, and
direct registers as an implicit operands (with Uses or Defs) but I want to
pass specific register.

Thank you very much for your time,
Arsen





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Hi Arsen,

> On Jun 19, 2014, at 10:43 PM, Arsen Hakobyan <artinetstudio at
gmail.com> wrote:
> 
> Hi all,
> 
> I want to generate an assembly instruction for my target using target
> description representation of the instruction. The problem is that I want
to
> add direct register to be chose as an output register for my target. Does
it
> possible to do with an instruction definition in TARGETInstrInfo.td  file? 
> May be someone could help with an example?
If I understood correctly, you want your instruction to define a specific
register.
If yes, you can achieve this by creating a specialized singleton register class
with the register you want and use it in the td file.
E.g., in yourTargetRegisterInfo.td:
def MyReg : RegisterClass<“MyTarget”, [Related Types], MySize, (add
MyReg)>;

in yourTargetInstrInfo.td:
def MyInstr […] (outs MyReg:$Rd) […]

The ARM target does something similar for SP. Look for GPRsp.

Cheers,
-Quentin
> 
> Currently I have seen that we can pass the name of the registers'
group, and
> direct registers as an implicit operands (with Uses or Defs) but I want to
> pass specific register.
> 
> Thank you very much for your time,
> Arsen
> 
> 
> 
> 
> 
> --
> View this message in context:
http://llvm.1065342.n5.nabble.com/Passing-specific-register-for-an-Instruction-in-target-description-files-tp69662.html
> Sent from the LLVM - Dev mailing list archive at Nabble.com.
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
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Hi Quentin,

Many thanks for your response. I will try to use that approach.
Arsen



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On Mon, Jun 30, 2014 at 02:40:43AM -0700, Quentin Colombet
wrote:
> Hi Arsen,
> 
> 
> > On Jun 19, 2014, at 10:43 PM, Arsen Hakobyan <artinetstudio at
gmail.com> wrote:
> > 
> > Hi all,
> > 
> > I want to generate an assembly instruction for my target using target
> > description representation of the instruction. The problem is that I
want to
> > add direct register to be chose as an output register for my target.
Does it
> > possible to do with an instruction definition in TARGETInstrInfo.td 
file?
> > May be someone could help with an example?
> 
> If I understood correctly, you want your instruction to define a specific
register.
> If yes, you can achieve this by creating a specialized singleton register
class with the register you want and use it in the td file.
> E.g., in yourTargetRegisterInfo.td:
> def MyReg : RegisterClass<“MyTarget”, [Related Types], MySize, (add
MyReg)>;
> 
> in yourTargetInstrInfo.td:
> def MyInstr […] (outs MyReg:$Rd) […]
> 
> The ARM target does something similar for SP. Look for GPRsp.
> 
If you use this approach, you may run into issues if the scheduler decides
to put two instructions that write to this register class in a row.  In this
case you will either need to implement spilling or the register allocator will
run out of registers.

The other way to solves this is to use the CustomInserter to force the
instruction
to use the register you want.

-Tom

> Cheers,
> -Quentin
> 
> > 
> > Currently I have seen that we can pass the name of the registers'
group, and
> > direct registers as an implicit operands (with Uses or Defs) but I
want to
> > pass specific register.
> > 
> > Thank you very much for your time,
> > Arsen
> > 
> > 
> > 
> > 
> > 
> > --
> > View this message in context:
http://llvm.1065342.n5.nabble.com/Passing-specific-register-for-an-Instruction-in-target-description-files-tp69662.html
> > Sent from the LLVM - Dev mailing list archive at Nabble.com.
> > _______________________________________________
> > LLVM Developers mailing list
> > LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> 
> 
> _______________________________________________
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