Arsen Hakobyan
2014-Jun-10 13:21 UTC
[LLVMdev] Regarding Instruction definition in LLVM backend
Hi Tim, Thank you for your response. I need that immediate value latter to concatenate to registers' names (which I am doing during assembly printing). Also just Updating some status for my questioin: I have continued with using *Defs* list. It allows me to keep Registers as an implicit operands of /*MachineInstr*/ and later during its lowering pass them to the /*MCInstr*/. Now seems I need only to change */printInstruction()/* function to Emit this instructions in appropriate way. For that I need to change /*utils/TableGen/AsmWriterEmitter.cpp: AsmWriterEmitter::EmitPrintInstruction*/ to generate appropriate code in "/TARGETGenAsmWriter.inc/" file. But I am still thinking that there should be a way to not pass the registers as an implicit operands. So other approaches will be appreciated. Thanks, Arsen -- View this message in context: http://llvm.1065342.n5.nabble.com/Regarding-Instruction-definition-in-LLVM-backend-tp69310p69318.html Sent from the LLVM - Dev mailing list archive at Nabble.com.
Tim Northover
2014-Jun-10 13:46 UTC
[LLVMdev] Regarding Instruction definition in LLVM backend
> I need that immediate value latter to concatenate to registers' names (which > I am doing during assembly printing).That really sounds like an odd implementation. Are your other instructions more normal (i.e. proper instance of RegisterClass, non-trivial (outs ...) and (ins ...), printing operands mostly handled by LLVM, ...)? If not, you really should be trying to follow that convention. This approach just isn't going to work in LLVM. On the other hand, if they are, what makes this MOV special? It looks like it's only that you have a really odd intrinsic you're trying to define? Or is it that MYREG1_NAME and MYREG2_NAME aren't your usual general purpose registers, and actually more like system control placeholders? AArch64, for example, has "mrs x0, TPIDR_EL0" to read the thread-specific base address; x0 is normal, but TPIDR_EL0 isn't a register LLVM should be tracking; it's more of an immediate with a convenient textual form. Either way, I think there are other ways to handle an intrinsic like that, but we need to know more details to say what they are. Cheers. Tim.
Arsen Hakobyan
2014-Jun-11 10:40 UTC
[LLVMdev] Regarding Instruction definition in LLVM backend
Hi Tim, Many thanks for your thoughts. Actually I have implemented it with the approach I choose (using Defs and then changing the assembly printer to emit the MCInstr in an appropriate way). And seems that works for me now. Actually I need to have finally assembly code with mov MYREG1_NAME_88 MYREG2_NAME_88 where 88 is an immediate argument value of the built-in function. This is needed for my target which can understand this kind of registers. Thank you again, Tim, for your time. Arsen -- View this message in context: http://llvm.1065342.n5.nabble.com/Regarding-Instruction-definition-in-LLVM-backend-tp69310p69346.html Sent from the LLVM - Dev mailing list archive at Nabble.com.