llvm dev - Jun 2014 - [LLVMdev] Inline assembly in LLVM backend

Hi all,
I need to support basic and extended inline assembly for a VLIW
architecture. It can have upto 3 instruction issues and hence I have a VLIW
scheduler. If I handle this traditionally in AsmPrinter, then the inline
assembly programmer has to provide scheduled instructions. However, I
cannot put the burden of scheduling on inline assembly programmer. So I
intend to process the unscheduled inline assembly statements before the
scheduler and after the register allocator. Is this a good design to follow?
I'm allowing branch instructions which means I need to modify CFG. I intend
to create new machine basic blocks and add the corresponding successors.
However I won't be updating the use-def chain or the live variable
information. Will this affect the analysis such as AliasAnalysis and
MachineDominatorTree construction?

Regards,
Vishwa Prakash A
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Hi Vishwa,
You would need to make sure that the inline assembly code that contains 
a branch is recognized as a terminator (which is now a bit in the 
instruction descriptor).

Can you use intrinsics instead of inline assembly?  That would make 
things a lot easier.

-K

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