I looked at this briefly, I think it causes some mistakes that get reversed later in fixupReg. The disassembler design is a bit of a mess with regards to prefixes and operand size. On Tue, Apr 1, 2014 at 4:43 PM, Jun Koi <junkoi2004 at gmail.com> wrote:> > > > On Mon, Mar 31, 2014 at 11:48 PM, Jun Koi <junkoi2004 at gmail.com> wrote: > >> Hi, >> >> In file X86DisassemblerDecoder.c, we have function readPrefixes() with >> below code: >> >> ..... >> } else if (insn->mode == MODE_32BIT) { >> insn->registerSize = (hasOpSize ? 2 : 4); >> insn->addressSize = (hasAdSize ? 2 : 4); >> insn->displacementSize = (hasAdSize ? 2 : 4); >> insn->immediateSize = (hasOpSize ? 2 : 4); >> } >> .... >> >> This is confused to me: so we have registerSize to be either 2 or 4 bytes. >> But we might have instruction like: >> >> adc al, 0x89 >> >> This case we should have registerSize = 1 for AL. So is this a bug, or I >> am misunderstanding the meaning of this "registerSize" ?? >> >> > any help please? > > thanks. > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > >-- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140401/cbe8d415/attachment.html>
On Wed, Apr 2, 2014 at 8:22 AM, Craig Topper <craig.topper at gmail.com> wrote:> I looked at this briefly, I think it causes some mistakes that get > reversed later in fixupReg. >so this is indeed a bug, right?> The disassembler design is a bit of a mess with regards to prefixes and > operand size. >do you mean the bug related to "0x66 0xf2" sequence? any hope to get it fixed? thanks, Jun> > On Tue, Apr 1, 2014 at 4:43 PM, Jun Koi <junkoi2004 at gmail.com> wrote: > >> >> >> >> On Mon, Mar 31, 2014 at 11:48 PM, Jun Koi <junkoi2004 at gmail.com> wrote: >> >>> Hi, >>> >>> In file X86DisassemblerDecoder.c, we have function readPrefixes() with >>> below code: >>> >>> ..... >>> } else if (insn->mode == MODE_32BIT) { >>> insn->registerSize = (hasOpSize ? 2 : 4); >>> insn->addressSize = (hasAdSize ? 2 : 4); >>> insn->displacementSize = (hasAdSize ? 2 : 4); >>> insn->immediateSize = (hasOpSize ? 2 : 4); >>> } >>> .... >>> >>> This is confused to me: so we have registerSize to be either 2 or 4 >>> bytes. >>> But we might have instruction like: >>> >>> adc al, 0x89 >>> >>> This case we should have registerSize = 1 for AL. So is this a bug, or I >>> am misunderstanding the meaning of this "registerSize" ?? >>> >>> >> any help please? >> >> thanks. >> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> >> > > > -- > ~Craig >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140402/a8a76760/attachment.html>
On Tue, Apr 1, 2014 at 7:38 PM, Jun Koi <junkoi2004 at gmail.com> wrote:> > > > On Wed, Apr 2, 2014 at 8:22 AM, Craig Topper <craig.topper at gmail.com>wrote: > >> I looked at this briefly, I think it causes some mistakes that get >> reversed later in fixupReg. >> > > so this is indeed a bug, right? >I can't prove that it causes any bad behavior. Can you?> > > >> The disassembler design is a bit of a mess with regards to prefixes and >> operand size. >> > > do you mean the bug related to "0x66 0xf2" sequence? any hope to get it > fixed? >It's a pretty fundamental flaw in the disassembler's design. The "repne" when it gets printed is treated as an instruction itself by the assembly printer and everything else. With the current design, there's really no way to get that to emit and to get the 0x66 to bind to the "scas". I would like to fix it, but I'll need to devote some time to do it that I don't have right now.> > > thanks, > Jun > > > > > > > > > >> >> On Tue, Apr 1, 2014 at 4:43 PM, Jun Koi <junkoi2004 at gmail.com> wrote: >> >>> >>> >>> >>> On Mon, Mar 31, 2014 at 11:48 PM, Jun Koi <junkoi2004 at gmail.com> wrote: >>> >>>> Hi, >>>> >>>> In file X86DisassemblerDecoder.c, we have function readPrefixes() with >>>> below code: >>>> >>>> ..... >>>> } else if (insn->mode == MODE_32BIT) { >>>> insn->registerSize = (hasOpSize ? 2 : 4); >>>> insn->addressSize = (hasAdSize ? 2 : 4); >>>> insn->displacementSize = (hasAdSize ? 2 : 4); >>>> insn->immediateSize = (hasOpSize ? 2 : 4); >>>> } >>>> .... >>>> >>>> This is confused to me: so we have registerSize to be either 2 or 4 >>>> bytes. >>>> But we might have instruction like: >>>> >>>> adc al, 0x89 >>>> >>>> This case we should have registerSize = 1 for AL. So is this a bug, or >>>> I am misunderstanding the meaning of this "registerSize" ?? >>>> >>>> >>> any help please? >>> >>> thanks. >>> >>> _______________________________________________ >>> LLVM Developers mailing list >>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >>> >>> >> >> >> -- >> ~Craig >> > >-- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140401/8b85d520/attachment.html>