llvm dev - Feb 2014 - [LLVMdev] Bug? LLVM X86 -m32 generates 64bit register in movd

Hi,

 

I am getting a weird situation. The –m32 x86 generates an instruction using

64bit registers.

 

The compiler I used is 

clang version 3.5 (trunk 198389)

Target: x86_64-unknown-linux-gnu

Thread model: posix

 

# BB#10:                                # %land.rhs.i

                cvttsd2si              %xmm0, %eax

                xorps     %xmm1, %xmm1

                cvtsi2sdl               %eax, %xmm1

                cmpeqsd             %xmm0, %xmm1

                movd    %xmm1, %rcx  ß-- 64bit registers            

                andq      $1, %rcx

                jmp        .LBB172_11

 

movd is generated after –O1 is used. –O0 has no this problem.

 

Could anyone let me know if this is a bug that has been fixed.

 

Thanks,

 

Yin 

-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20140207/4b370eec/attachment.html>

Hi Yin,
> movd is generated after –O1 is used. –O0 has no this problem.
>
> Could anyone let me know if this is a bug that has been fixed.
I don't see any recent changes in the area, but it's impossible to say
for certain without a test case.

Can you attach either a C or .ll file that demonstrates the issue?

Cheers.

Tim.