llvm dev - Apr 2011 - [LLVMdev] Instructions with register constraints

For any instruction, a list of constraints can be specified, like:
let Constraints = "$dst = $lhs" in
...

 I checked the existing backends and I didn't notice any complex
constraints: basically "Constraints" keyword is used to force 1
operand
register to be the same as  another one.
I am wondering if there is any way to express more complicated constraints
like for example:
- if $lhs is either r0,r1,r2,r3 then $dst should also be in the set
{r0,r1,r2,r3}
- if $lhs is either r4,r5,r6,r7 then $dst should also be in the set {r4, r5,
r6, r7}
...

  Thank you !

  Damien
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On Apr 8, 2011, at 10:13 AM, Damien Vincent wrote:
> 
>  For any instruction, a list of constraints can be specified, like:
> let Constraints = "$dst = $lhs" in 
> ...
> 
>  I checked the existing backends and I didn't notice any complex
constraints: basically "Constraints" keyword is used to force 1
operand register to be the same as  another one.
> I am wondering if there is any way to express more complicated constraints
like for example:
> - if $lhs is either r0,r1,r2,r3 then $dst should also be in the set
{r0,r1,r2,r3}
> - if $lhs is either r4,r5,r6,r7 then $dst should also be in the set {r4,
r5, r6, r7}
Not at the moment, no. The only constraints supported are the
"tied-to" constraint you indicate above and the
"@earlyclobber" constraint which indicates an output register that
cannot also be allocated to one of the instruction inputs.

See CodeGenInstruction.cpp in utils/TableGen for the gory details.

Regards,
-Jim