llvm dev - Jun 2009 - [LLVMdev] A question about backend implementation of instructions with special register allocation needs.

I stumbled upon the following problem when truing to support the 
following non-standard  instruction extensions to a MIPS like architecture:

1.)
    double store :   Ri,Ri+1  are stored to the memory at address 
specified by (Rj).
    Here the instruction encoding includes only  'i' but it implicitly 
uses also Ri+1.   I can define a special intrinsic for this in "C"
   such as store64(int v1,int v2,int *address), but then I run into 
problems with the register allocation as I need to tell it that
   I want to use Ri and Ri+1 an not just any general pair of registers ....
2.) Just  any kind of instruction with register update semantics. like  
for simplicity sake suppose I have  an instruction such as
      which updates Ri , such as    Ri  <-  somefunc(Ri,Rj).
     can I specify the same argument as both input and output in the 
tablegen instrinfo.td and just hope it works ?

My general question, is if there is some general  way to tell the 
register allocator about constraints when choosing the registers
it allocates because of the requirements of some instructions....

Hello, Gil
>    double store :   Ri,Ri+1  are stored to the memory at address
> specified by (Rj).
Why don't define new register class for such sort of things with wide
"virtual" registers containing Ri,Ri+1 as subregs? You can emit such
wide stores and even do some post-pass to convert narrow stores into
wide one (look into ARM's multiple store pass). Recently added
regalloc hints will even help regalloc to generate narrow stores which
can be turned into wide later.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University