Linux_hpc_swstack - Jun 2009 - Feature Request: BIOS Tools and Improved BIOS/FW Release Notes

Hi,

were there any results of the flashrom evaluation?
As one of the main authors of flashrom, I''m very interested in what we
can do to make flashrom the preferred choice for BIOS updates.

Regards,
Carl-Daniel

On Mon Sep 8 13:03:33 PDT 2008, Matthew Bohnsack wrote:
> Requirement A. Linux commandline utilities for BIOS read/write
> ===============================================================> 
> Description:
> 
> We need a Linux commandline utility that:
> 
>       * Can read a BIOS image from a node''s EEPROM, including
firmware
>         revision and settings and then write this image to a file.
>       * Can write a previously created BIOS image to a node''s
EEPROM.
>       * Will not overwrite node VPD.  E.g., if I save a BIOS image from
>         node1 to disk and then write that image to node2, node1 and
>         node2 should retain unique VPD information such as serial
>         numbers that are viewable from dmidecode, IMPI utilities, etc.
>       * Works on current Harpertown-based X6250 blades
>       * Works on future Gainestown-based X???? blades
> 
> Note that while this utility would enable BIOS revision updates, this
> type of update is currently possible via a SMASH/TFTP process that can
> be easily automated.  I.e., it''s making the BIOS settings changes
that''s
> today''s key missing piece of functionality.
> 
> Preferred Implementation:
> 
> We prefer an OpenSource solution running from Linux userspace, based on
> coreboot''s flashrom.  See notes about tests performed with this
tool at
> the end of this note and the website: http://www.coreboot.org/Flashrom

Carl-Daniel,

Thanks very much for your inquiry!  We''d still very much prefer the use
of something like flashROM, but the vendor didn''t support this on their
x6275 Gainestown/Nehalem blades.  They offered up a proprietary alternative
called suncfg for settings, and another proprietary process through their
service processors to update the BIOS code.  We are successful with these tool
so far.

I honestly haven''t tested flashROM since we received our Nehalem
machines, but your note prompted me to do so.  My results so far are promising,
but I''m don''t have time at the moment for much more testing. 
Hopefully we can do some more testing later this week.

Thanks again,

-Matthew

# ./flashrom -r outputfile.dat
flashrom v0.9.0-r636
No coreboot table found.
Found chipset "Intel ICH10R", enabling flash write... OK.
This chipset supports the following protocols: LPC,FWH,SPI.
Calibrating delay loop... OK.
Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address
0xffe00000.
Found chip "SST SST49LF008A" (1024 KB, FWH) at physical address
0xfff00000.
Multiple flash chips were detected: SST25VF016B SST49LF008A
Please specify which chip to use with the -c <chipname> option.

# ./flashrom -c SST49LF008A -r outputfile-SST49LF008A.dat
flashrom v0.9.0-r636
No coreboot table found.
Found chipset "Intel ICH10R", enabling flash write... OK.
This chipset supports the following protocols: LPC,FWH,SPI.
Calibrating delay loop... OK.
Found chip "SST SST49LF008A" (1024 KB, FWH) at physical address
0xfff00000.
Reading flash... done.

# ./flashrom -c SST25VF016B -r outputfile-SST25VF016B.dat
flashrom v0.9.0-r636
No coreboot table found.
Found chipset "Intel ICH10R", enabling flash write... OK.
This chipset supports the following protocols: LPC,FWH,SPI.
Calibrating delay loop... OK.
Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address
0xffe00000.
Reading flash... done.


-----Original Message-----
From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net] 
Sent: Monday, June 29, 2009 7:14 AM
To: linux_hpc_swstack at lists.lustre.org
Cc: Matthew Bohnsack
Subject: [Linux_hpc_swstack] Feature Request: BIOS Tools and Improved BIOS/FW
Release Notes

Hi,

were there any results of the flashrom evaluation?
As one of the main authors of flashrom, I''m very interested in what we
can do to make flashrom the preferred choice for BIOS updates.

Regards,
Carl-Daniel

On Mon Sep 8 13:03:33 PDT 2008, Matthew Bohnsack wrote:
> Requirement A. Linux commandline utilities for BIOS read/write 
> ===============================================================> 
> Description:
> 
> We need a Linux commandline utility that:
> 
>       * Can read a BIOS image from a node''s EEPROM, including
firmware
>         revision and settings and then write this image to a file.
>       * Can write a previously created BIOS image to a node''s
EEPROM.
>       * Will not overwrite node VPD.  E.g., if I save a BIOS image from
>         node1 to disk and then write that image to node2, node1 and
>         node2 should retain unique VPD information such as serial
>         numbers that are viewable from dmidecode, IMPI utilities, etc.
>       * Works on current Harpertown-based X6250 blades
>       * Works on future Gainestown-based X???? blades
> 
> Note that while this utility would enable BIOS revision updates, this 
> type of update is currently possible via a SMASH/TFTP process that can 
> be easily automated.  I.e., it''s making the BIOS settings changes 
> that''s today''s key missing piece of functionality.
> 
> Preferred Implementation:
> 
> We prefer an OpenSource solution running from Linux userspace, based 
> on coreboot''s flashrom.  See notes about tests performed with this
> tool at the end of this note and the website: 
> http://www.coreboot.org/Flashrom

Hi Matthew,

thank you very much for your speedy response!
The dual flash chip detection looks a bit suspicious because the mapped
ranges of both flash chips overlap. If that is indeed correct, flashrom
may need special code to handle the situation (AFAIK the behaviour of
the chipset is undefined for overlapping dual flash, but I''ll reread
the
data sheets).

Would you mind mailing me the output of
"flashrom -V"
which runs detection only, but has lots of verbose output allowing me to
diagnose the exact flash configuration. The output will very likely have
"id1 is normal flash content, id2 is normal flash content" for the
SST49LF008A probe if the SST49LF008A is not there for real.

One thing we''re currently working on is partial reflashing support
which
should give you the VPD preservation you need. Unfortunately, that
feature will probably not make it into the soon to be released flashrom
0.9.1, but we have several developers interested in this (and even some
pending patches which need verification).

Your configuration data may be stored in flash or NVRAM. For the latter,
we have nvramtool at http://www.coreboot.org/Nvramtool which should
allow dumping NVRAM contents for proprietary BIOS and coreboot alike.

Take your time with testing. I won''t disappear overnight. ;-)
Please note that I''ll be offline from Tuesday to Thursday to meet the
deadline for a paper I''m working on. Once that is done, you have my
full
attention again.


Regards,
Carl-Daniel

On 29.06.2009 16:44, Bohnsack, Matthew Paul wrote:
> Carl-Daniel,
>
> Thanks very much for your inquiry!  We''d still very much prefer
the use of something like flashROM, but the vendor didn''t support this
on their x6275 Gainestown/Nehalem blades.  They offered up a proprietary
alternative called suncfg for settings, and another proprietary process through
their service processors to update the BIOS code.  We are successful with these
tool so far.
>
> I honestly haven''t tested flashROM since we received our Nehalem
machines, but your note prompted me to do so.  My results so far are promising,
but I''m don''t have time at the moment for much more testing. 
Hopefully we can do some more testing later this week.
>
> Thanks again,
>
> -Matthew
>
> # ./flashrom -r outputfile.dat
> flashrom v0.9.0-r636
> No coreboot table found.
> Found chipset "Intel ICH10R", enabling flash write... OK.
> This chipset supports the following protocols: LPC,FWH,SPI.
> Calibrating delay loop... OK.
> Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address
0xffe00000.
> Found chip "SST SST49LF008A" (1024 KB, FWH) at physical address
0xfff00000.
> Multiple flash chips were detected: SST25VF016B SST49LF008A
> Please specify which chip to use with the -c <chipname> option.
>
> # ./flashrom -c SST49LF008A -r outputfile-SST49LF008A.dat
> flashrom v0.9.0-r636
> No coreboot table found.
> Found chipset "Intel ICH10R", enabling flash write... OK.
> This chipset supports the following protocols: LPC,FWH,SPI.
> Calibrating delay loop... OK.
> Found chip "SST SST49LF008A" (1024 KB, FWH) at physical address
0xfff00000.
> Reading flash... done.
>
> # ./flashrom -c SST25VF016B -r outputfile-SST25VF016B.dat
> flashrom v0.9.0-r636
> No coreboot table found.
> Found chipset "Intel ICH10R", enabling flash write... OK.
> This chipset supports the following protocols: LPC,FWH,SPI.
> Calibrating delay loop... OK.
> Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address
0xffe00000.
> Reading flash... done.
>
>
> -----Original Message-----
> From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net] 
> Sent: Monday, June 29, 2009 7:14 AM
> To: linux_hpc_swstack at lists.lustre.org
> Cc: Matthew Bohnsack
> Subject: [Linux_hpc_swstack] Feature Request: BIOS Tools and Improved
BIOS/FW Release Notes
>
> Hi,
>
> were there any results of the flashrom evaluation?
> As one of the main authors of flashrom, I''m very interested in
what we can do to make flashrom the preferred choice for BIOS updates.
>
> Regards,
> Carl-Daniel
>
> On Mon Sep 8 13:03:33 PDT 2008, Matthew Bohnsack wrote:
>   
>> Requirement A. Linux commandline utilities for BIOS read/write 
>> ===============================================================>>
>> Description:
>>
>> We need a Linux commandline utility that:
>>
>>       * Can read a BIOS image from a node''s EEPROM, including
firmware
>>         revision and settings and then write this image to a file.
>>       * Can write a previously created BIOS image to a node''s
EEPROM.
>>       * Will not overwrite node VPD.  E.g., if I save a BIOS image from
>>         node1 to disk and then write that image to node2, node1 and
>>         node2 should retain unique VPD information such as serial
>>         numbers that are viewable from dmidecode, IMPI utilities, etc.
>>       * Works on current Harpertown-based X6250 blades
>>       * Works on future Gainestown-based X???? blades
>>
>> Note that while this utility would enable BIOS revision updates, this 
>> type of update is currently possible via a SMASH/TFTP process that can 
>> be easily automated.  I.e., it''s making the BIOS settings
changes
>> that''s today''s key missing piece of functionality.
>>
>> Preferred Implementation:
>>
>> We prefer an OpenSource solution running from Linux userspace, based 
>> on coreboot''s flashrom.  See notes about tests performed with
this
>> tool at the end of this note and the website: 
>> http://www.coreboot.org/Flashrom
>>

Carl-Daniel,

The output of "flashrom -V" that you requested is attached.  Thanks
for the additional information!

-Matthew

Matthew Bohnsack
Desk Phone: 505-284-1661 (Mountain Time)
Pager: 505-530-0163

-----Original Message-----
From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net] 
Sent: Monday, June 29, 2009 9:11 AM
To: Bohnsack, Matthew Paul
Cc: linux_hpc_swstack at lists.lustre.org; Matthew Bohnsack; Epperson, Marcus R;
Maestas, Christopher Daniel; Monk, Stephen; Ogden, Jeffry Brandon; Beggio,
Christopher Allen
Subject: Re: [Linux_hpc_swstack] Feature Request: BIOS Tools and Improved
BIOS/FW Release Notes

Hi Matthew,

thank you very much for your speedy response!
The dual flash chip detection looks a bit suspicious because the mapped ranges
of both flash chips overlap. If that is indeed correct, flashrom may need
special code to handle the situation (AFAIK the behaviour of the chipset is
undefined for overlapping dual flash, but I''ll reread the data sheets).

Would you mind mailing me the output of
"flashrom -V"
which runs detection only, but has lots of verbose output allowing me to
diagnose the exact flash configuration. The output will very likely have
"id1 is normal flash content, id2 is normal flash content" for the
SST49LF008A probe if the SST49LF008A is not there for real.

One thing we''re currently working on is partial reflashing support
which should give you the VPD preservation you need. Unfortunately, that feature
will probably not make it into the soon to be released flashrom 0.9.1, but we
have several developers interested in this (and even some pending patches which
need verification).

Your configuration data may be stored in flash or NVRAM. For the latter, we have
nvramtool at http://www.coreboot.org/Nvramtool which should allow dumping NVRAM
contents for proprietary BIOS and coreboot alike.

Take your time with testing. I won''t disappear overnight. ;-) Please
note that I''ll be offline from Tuesday to Thursday to meet the deadline
for a paper I''m working on. Once that is done, you have my full
attention again.


Regards,
Carl-Daniel

On 29.06.2009 16:44, Bohnsack, Matthew Paul wrote:
> Carl-Daniel,
>
> Thanks very much for your inquiry!  We''d still very much prefer
the use of something like flashROM, but the vendor didn''t support this
on their x6275 Gainestown/Nehalem blades.  They offered up a proprietary
alternative called suncfg for settings, and another proprietary process through
their service processors to update the BIOS code.  We are successful with these
tool so far.
>
> I honestly haven''t tested flashROM since we received our Nehalem
machines, but your note prompted me to do so.  My results so far are promising,
but I''m don''t have time at the moment for much more testing. 
Hopefully we can do some more testing later this week.
>
> Thanks again,
>
> -Matthew
>
> # ./flashrom -r outputfile.dat
> flashrom v0.9.0-r636
> No coreboot table found.
> Found chipset "Intel ICH10R", enabling flash write... OK.
> This chipset supports the following protocols: LPC,FWH,SPI.
> Calibrating delay loop... OK.
> Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address
0xffe00000.
> Found chip "SST SST49LF008A" (1024 KB, FWH) at physical address
0xfff00000.
> Multiple flash chips were detected: SST25VF016B SST49LF008A Please 
> specify which chip to use with the -c <chipname> option.
>
> # ./flashrom -c SST49LF008A -r outputfile-SST49LF008A.dat flashrom 
> v0.9.0-r636 No coreboot table found.
> Found chipset "Intel ICH10R", enabling flash write... OK.
> This chipset supports the following protocols: LPC,FWH,SPI.
> Calibrating delay loop... OK.
> Found chip "SST SST49LF008A" (1024 KB, FWH) at physical address
0xfff00000.
> Reading flash... done.
>
> # ./flashrom -c SST25VF016B -r outputfile-SST25VF016B.dat flashrom 
> v0.9.0-r636 No coreboot table found.
> Found chipset "Intel ICH10R", enabling flash write... OK.
> This chipset supports the following protocols: LPC,FWH,SPI.
> Calibrating delay loop... OK.
> Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address
0xffe00000.
> Reading flash... done.
>
>
> -----Original Message-----
> From: Carl-Daniel Hailfinger 
> [mailto:c-d.hailfinger.devel.2006 at gmx.net]
> Sent: Monday, June 29, 2009 7:14 AM
> To: linux_hpc_swstack at lists.lustre.org
> Cc: Matthew Bohnsack
> Subject: [Linux_hpc_swstack] Feature Request: BIOS Tools and Improved 
> BIOS/FW Release Notes
>
> Hi,
>
> were there any results of the flashrom evaluation?
> As one of the main authors of flashrom, I''m very interested in
what we can do to make flashrom the preferred choice for BIOS updates.
>
> Regards,
> Carl-Daniel
>
> On Mon Sep 8 13:03:33 PDT 2008, Matthew Bohnsack wrote:
>   
>> Requirement A. Linux commandline utilities for BIOS read/write 
>> ===============================================================>>
>> Description:
>>
>> We need a Linux commandline utility that:
>>
>>       * Can read a BIOS image from a node''s EEPROM, including
firmware
>>         revision and settings and then write this image to a file.
>>       * Can write a previously created BIOS image to a node''s
EEPROM.
>>       * Will not overwrite node VPD.  E.g., if I save a BIOS image from
>>         node1 to disk and then write that image to node2, node1 and
>>         node2 should retain unique VPD information such as serial
>>         numbers that are viewable from dmidecode, IMPI utilities, etc.
>>       * Works on current Harpertown-based X6250 blades
>>       * Works on future Gainestown-based X???? blades
>>
>> Note that while this utility would enable BIOS revision updates, this 
>> type of update is currently possible via a SMASH/TFTP process that 
>> can be easily automated.  I.e., it''s making the BIOS settings
changes
>> that''s today''s key missing piece of functionality.
>>
>> Preferred Implementation:
>>
>> We prefer an OpenSource solution running from Linux userspace, based 
>> on coreboot''s flashrom.  See notes about tests performed with
this
>> tool at the end of this note and the website:
>> http://www.coreboot.org/Flashrom
>>     

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