Hi folks,
I have several systems using T7200 mobile CPUs running under 7-stable.
However, EST does not recognize the cpus. When loading cpufreq I get:
---
Jan 18 23:18:14 comet kernel: est1: <Enhanced SpeedStep Frequency Control>
on cpu1
Jan 18 23:18:14 comet kernel: est: CPU supports Enhanced
Speedstep, but is not recognized.
Jan 18 23:18:14 comet kernel: est: cpu_vendor GenuineIntel, msr
6130c2906000c29
Jan 18 23:18:14 comet kernel: device_attach: est1 attach returned 6
Jan 18 23:18:14 comet kernel: p4tcc0: <CPU Frequency Thermal Control> on
cpu0
Jan 18 23:18:14 comet kernel: est1: <Enhanced SpeedStep Frequency
Control> on cpu1
Jan 18 23:18:14 comet kernel: est: CPU supports Enhanced
Control> Speedstep, but is not recognized.
Jan 18 23:18:14 comet kernel: Control> est: cpu_vendor GenuineIntel,
msr 6130c2906000c29
Jan 18 23:18:14 comet kernel: device_attach: est1 attach returned 6
Jan 18 23:18:14 comet kernel: p4tcc1: <CPU Frequency Thermal Control> on
cpu1
Jan 18 23:18:14 comet kernel: est1: <Enhanced SpeedStep Frequency
Control> on cpu1
Jan 18 23:18:14 comet kernel: est: CPU supports Enhanced Control>
Speedstep, but is not recognized.
Jan 18 23:18:14 comet kernel: est: cpu_vendor GenuineIntel, msr
6130c2906000c29
Jan 18 23:18:14 comet kernel: device_attach: est1 attach returned 6
Jan 18 23:18:14 comet kernel: est1: <Enhanced SpeedStep Frequency Control>
on cpu1
Jan 18 23:18:14 comet kernel: est: CPU supports Enhanced Speedstep,
but is not recognized.
Jan 18 23:18:14 comet kernel: est: cpu_vendor GenuineIntel, msr
6130c2906000c29 Jan 18 23:18:14 comet kernel: device_attach: est1 attach
returned 6
---
Here is some (hopefully useful :-) excerpt from my dmesg:
---
Copyright (c) 1992-2007 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
The Regents of the University of California. All rights reserved.
FreeBSD is a registered trademark of The FreeBSD Foundation.
FreeBSD 7.0-BETA4 #0: Fri Dec 14 21:02:47 CET 2007
root@comet.terra.ger:/usr/obj/usr/src/sys/COMET.7
can't re-use a leaf (siots)!
can't re-use a leaf (conspeed)!
can't re-use a leaf (gdbspeed)!
can't re-use a leaf (conrclk)!
Timecounter "i8254" frequency 1193182 Hz quality 0
CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz (1999.00-MHz
686-class CPU) Origin = "GenuineIntel" Id = 0x6f6 Stepping = 6
Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
Features2=0xe3bd<SSE3,RSVD2,MON,DS_CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM>
AMD Features=0x20100000<NX,LM>
AMD Features2=0x1<LAHF>
Cores per package: 2
real memory = 2137915392 (2038 MB)
avail memory = 2086670336 (1990 MB)
ACPI APIC Table: <IntelR AWRDACPI>
FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs
cpu0 (BSP): APIC ID: 0
cpu1 (AP): APIC ID: 1
pnpbios: Bad PnP BIOS data checksum
ioapic0: Changing APIC ID to 2
ioapic0 <Version 2.0> irqs 0-23 on motherboard
[...]
acpi0: <IntelR AWRDACPI> on motherboard
acpi0: [ITHREAD]
acpi0: Power Button (fixed)
acpi0: reservation of 0, a0000 (3) failed
acpi0: reservation of 100000, 7f5e0000 (3) failed
Timecounter "ACPI-fast" frequency 3579545 Hz quality 1000
acpi_timer0: <24-bit timer at 3.579545MHz> port 0x408-0x40b on acpi0
cpu0: <ACPI CPU> on acpi0
acpi_perf0: <ACPI CPU Frequency Control> on cpu0
cpu1: <ACPI CPU> on acpi0
acpi_button0: <Power Button> on acpi0
[...]
SMP: AP CPU #1 Launched!
---
When I start powerd with cpufreq loaded like this, the machines
typically crash and reboot. I searched the web for a while to find a
solution for this, but without any success. Does anybody here have some
hints how to get speedstepping & co. to work properly?
cu
Gerrit
On Mon, Jan 21, 2008 at 05:16:06PM +0100, Gerrit K?hn wrote:> I have several systems using T7200 mobile CPUs running under 7-stable. > However, EST does not recognize the cpus. When loading cpufreq I get: > > --- > Jan 18 23:18:14 comet kernel: est1: <Enhanced SpeedStep Frequency Control> on cpu1 > Jan 18 23:18:14 comet kernel: est: CPU supports Enhanced Speedstep, but is not recognized. > Jan 18 23:18:14 comet kernel: est: cpu_vendor GenuineIntel, msr 6130c2906000c29 > Jan 18 23:18:14 comet kernel: device_attach: est1 attach returned 6 > ---I see identical behaviour on our Supermicro PDSMI+ systems, using E6420 CPUs, so I don't believe the problem is specific to your motherboard or certain Intel CPU models: CPU: Intel(R) Core(TM)2 CPU 6420 @ 2.13GHz (2128.01-MHz 686-class CPU) acpi0: <PTLTD RSDT> on motherboard acpi0: [ITHREAD] acpi0: Power Button (fixed) cpu0: <ACPI CPU> on acpi0 est0: <Enhanced SpeedStep Frequency Control> on cpu0 est: CPU supports Enhanced Speedstep, but is not recognized. est: cpu_vendor GenuineIntel, msr 82a082a0600082a device_attach: est0 attach returned 6 cpu1: <ACPI CPU> on acpi0 est1: <Enhanced SpeedStep Frequency Control> on cpu1 est: CPU supports Enhanced Speedstep, but is not recognized. est: cpu_vendor GenuineIntel, msr 82a082a0600082a device_attach: est1 attach returned 6 In the case of our servers, we usually turn EIST off (this one particular box has it enabled) because of the above problem -- but I'd much rather have it turned on to help save power. For a laptop or workstation, however, I can see this being an incredibly important feature. -- | Jeremy Chadwick jdc at parodius.com | | Parodius Networking http://www.parodius.com/ | | UNIX Systems Administrator Mountain View, CA, USA | | Making life hard for others since 1977. PGP: 4BD6C0CB |
On Monday 21 January 2008 11:16:06 am Gerrit K?hn wrote:> Hi folks, > > I have several systems using T7200 mobile CPUs running under 7-stable. > However, EST does not recognize the cpus. When loading cpufreq I get:You can try this patch. It won't add support for all of the levels, but it will support the current level and the highest level (IIRC). Index: est.c ==================================================================RCS file: /usr/cvs/src/sys/i386/cpufreq/est.c,v retrieving revision 1.11 diff -u -r1.11 est.c --- est.c 11 May 2006 17:35:44 -0000 1.11 +++ est.c 2 Oct 2007 18:04:58 -0000 @@ -38,6 +38,7 @@ #include <sys/systm.h> #include "cpufreq_if.h" +#include <machine/clock.h> #include <machine/md_var.h> #include <contrib/dev/acpica/acpi.h> @@ -70,6 +71,7 @@ struct est_softc { device_t dev; int acpi_settings; + int msr_settings; freq_info *freq_list; }; @@ -897,6 +899,7 @@ static int est_get_info(device_t dev); static int est_acpi_info(device_t dev, freq_info **freqs); static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs); +static int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs); static freq_info *est_get_current(freq_info *freq_list); static int est_settings(device_t dev, struct cf_setting *sets, int *count); static int est_set(device_t dev, const struct cf_setting *set); @@ -1031,11 +1034,13 @@ static int est_detach(device_t dev) { +#if 0 struct est_softc *sc; sc = device_get_softc(dev); - if (sc->acpi_settings) + if (sc->acpi_settings || sc->msr_settings) free(sc->freq_list, M_DEVBUF); +#endif return (ENXIO); } @@ -1059,6 +1064,9 @@ if (error) error = est_acpi_info(dev, &sc->freq_list); + if (error) + error = est_msr_info(dev, msr, &sc->freq_list); + if (error) { printf( "est: CPU supports Enhanced Speedstep, but is not recognized.\n" @@ -1149,6 +1157,77 @@ return (0); } +/* + * Flesh out a simple rate table containing the high and low frequencies + * based on the current clock speed and the upper 32 bits of the MSR. + */ +static int +est_msr_info(device_t dev, uint64_t msr, freq_info **freqs) +{ + struct est_softc *sc; + freq_info *fp; + int bus, freq, volts; + uint16_t id; + + if (strcmp("GenuineIntel", cpu_vendor) != 0) + return (EOPNOTSUPP); + + /* Figure out the bus clock. */ + freq = tsc_freq / 1000000; + id = msr >> 32; + bus = freq / (id >> 8); + device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus); + if (bus != 100 && bus != 133) { + /* We may be running on the low frequency. */ + id = msr >> 48; + bus = freq / (id >> 8); + device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus); + if (bus != 100 && bus != 133) + return (EOPNOTSUPP); + + /* Calculate high frequency. */ + id = msr >> 32; + freq = ((id >> 8) & 0xff) * bus; + } + + /* Fill out a new freq table containing just the high and low freqs. */ + sc = device_get_softc(dev); + fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO); + + /* First, the high frequency. */ + volts = id & 0xff; + if (volts != 0) { + volts <<= 4; + volts += 700; + } + fp[0].freq = freq; + fp[0].volts = volts; + fp[0].id16 = id; + fp[0].power = CPUFREQ_VAL_UNKNOWN; + device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq, + volts); + + /* Second, the low frequency. */ + id = msr >> 48; + freq = ((id >> 8) & 0xff) * bus; + volts = id & 0xff; + if (volts != 0) { + volts <<= 4; + volts += 700; + } + fp[1].freq = freq; + fp[1].volts = volts; + fp[1].id16 = id; + fp[1].power = CPUFREQ_VAL_UNKNOWN; + device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq, + volts); + + /* Table is already terminated due to M_ZERO. */ + sc->msr_settings = TRUE; + *freqs = fp; + return (0); +} + static freq_info * est_get_current(freq_info *freq_list) { -- John Baldwin